ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 226

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.10.4
19.10.5
8077H–AVR–12/09
ADDR - TWI Slave Address Register
DATA - TWI Slave Data Register
• Bit 0 - AP: Slave Address or Stop
The Slave Address or Stop (AP) flag indicates whether a valid address or a STOP condition
caused the last setting of the APIF in the STATUS register.
Table 19-8.
This register contains the TWI slave address used by the slave address match logic to deter-
mine if a master has addressed the slave. The 7 most significant bits (ADDR[7:1]) represents the
slave address and the least significant bit (ADDR[0]) is used for general call address recognition.
When ADDR[0] is set this enables general call address recognition logic so the device can
respond to a general address call that addresses all devices on the bus.
When using 10-bit addressing the address match logic only support hardware address recogni-
tion of the first byte of a 10-bit address. By setting ADDR[7:1] = "0b11110nn", 'nn' represents bit
9 and 8 for the slave address. The next byte received is bit 7 to 0 in the 10-bit address, and this
must be handled by software.
When the address match logic detects that a valid address byte is received, the APIF is set, and
the DIR flag is updated.
If the PMEN bit in CTRLA is set, the address match logic responds to all addresses transmitted
on the TWI bus. The ADDR register is not used in this mode.
The data (DATA) register is used when transmitting and received data. During data transfer,
data is shifted from/to the DATA register and to/from the bus. This implies that the DATA register
cannot be accessed during byte transfers, and this is protected in hardware. The Data register
can only be accessed when the SCL line is held low by the slave, i.e. when CLKHOLD is set.
When a master is reading data from the slave, data to send must be written to the DATA regis-
ter. The byte transfer is started when the Master start to clock the data byte from the slave,
followed by the slave receiving the acknowledge bit from the master. The DIF and the CLKHOLD
flag are set.
When a master write data to the slave the DIF and the CLKHOLD flag are set when one byte is
received in the DATA register. If Smart Mode is enabled, reading the DATA register will trigger
the bus operation as set by the ACKACT bit.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x03
Read/Write
Initial Value
AP
0
1
R/W
R/W
TWI slave address or stop
7
0
7
0
Description
A stop condition generated the interrupt on APIF
Address detection generated the interrupt on APIF
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
ADDR[7:0]
DATA[7:0]
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
0
XMEGA A
R/W
R/W
0
0
0
0
ADDR
DATA
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