ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 366

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.8
30.9
30.9.1
30.9.2
30.10 CRC Functionality
8077H–AVR–12/09
Protection of NVM
Preventing NVM Corruption
Write Corruption
Read Corruption
Alternative 2, fill the buffer before a Page Erase and Write:
To protect the Flash and EEPROM memories from write and/or read, Lock Bits can be set to
restrict access from external programmers and the Application Software. Refer to
Non-Volatile Memory Lock Bit Register” on page 29
and how to use them.
During periods when the V
result from a Flash memory read or write can be corrupt as supply voltage is too low for the CPU
and the Flash to operate properly.
To ensure that the voltage is correct during a complete write sequence to the Flash memory, the
BOD is automatically enabled by hardware when the write sequence starts. If a BOD reset
occurs, the programming sequence will be aborted immediately. If this happens, the NVM pro-
gramming should be restarted when the power is sufficient again in case the write sequence
failed or only partly succeeded.
The NVM can be read incorrectly if the supply voltage is too low so the CPU execute instructions
incorrectly. To ensure that this does not happen the BOD can be enabled.
It is possible to run an automatic Cyclic Redundancy Check (CRC) on the Flash Program Mem-
ory. This can be issued from external programming or software to do a CRC on the Application
Section, Boot Loader Section or a selected address range of the Flash.
Once the CRC is started, the CPU will be halted until the CRC is done and the checksum is
available in the NVM Data Register. The CRC takes one CPU Clock cycle per word that is
included in the CRC address range.
The polynomial that is used for CRC is fixed, and this is: x
• Perform a EEPROM Page Erase.
• Perform a EEPROM Page Write.
• Fill the EEPROM page buffer with the selected number of bytes.
• Perform an EEPROM Page Erase and Write.
CC
voltage is below the minimum operating voltage for the device, the
for details on the available Lock Bit settings
24
+ 4x
3
+ 3x +1.
XMEGA A
”LOCKBITS -
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