ATxmega256A3B Atmel Corporation, ATxmega256A3B Datasheet - Page 381

• Manufacturer Part Number: ATxmega256A3B
• Manufacturer: Atmel Corporation

Specifications of ATxmega256A3B

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 47
• Ext Interrupts: 49
• Usb Speed: No
• Usb Interface: No
• Spi: 8
• Twi (i2c): 2
• Uart: 6
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 16
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.12.1
30.12.2
30.12.2.1
30.12.2.2
30.12.3
8077H–AVR–12/09
CMD[6:0]
Flash Page Buffer
0x00
0x40
0x43
Enabling External Programming Interface
NVM Programming
NVM Commands
Addressing the NVM
NVM Busy
Commands / Operation
No Operation
Chip Erase
Read NVM
(1)
NVM programming from the PDI requires enabling, and this is one the following fashion.
When the NVMEN bit in the PDI STATUS register is set the NVM interface is active from the
PDI.
When the PDI NVM interface is enabled, all the memories in the device is memory-mapped in
the PDI address space. The PDI controller does not need to access the NVM controller's
address or data registers, but that the NVM controller must be loaded with the correct command
(i.e. to read from any NVM, the controller must be loaded with the NVM Read command before
trying to load data from the PDIBUS address space). For the reminder of this section all refer-
ences to reading and writing data or program memory addresses from PDI, refer to the memory
map as shown in
The PDI is always using byte addressing, hence all memory addresses must be byte addresses.
When filling the Flash or EEPROM page buffers, only the least significant bits of the address are
used to determine locations within the page buffer. Still, the complete memory mapped address
for the Flash or EEPROM page is required to ensure correct address mapping. The user must
pay attention to page boundaries for both page buffer loads and page buffer writes.
During programming (page erase and page write) when the NVM is busy, the complete NVM is
blocked for reading.
The NVM commands that can be used for accessing the NVM memories from external program-
ming are listed in
programming.
For external programming, the Trigger for Action Triggered Commands is to set the CMDEX bit
in the NVM CTRLA register (CMDEX). The Read Triggered Commands are triggered by a direct
or indirect Load instruction (LDS or LD) from the PDI (PDI Read). The Write Triggered Com-
mands is triggered by a direct or indirect Store instruction (STS or ST) from the PDI (PDI Write).
Section 30.12.3.1 on page 383
algorithm for each NVM operation. The commands are protected by the Lock Bits, and if Read
and Write Lock is set, only the Chip Erase and Flash CRC commands are available.
Table 30-5.
1. Load the RESET register in the PDI with 0x59 - the Reset Signature.
2. Load the correct NVM key in the PDI.
3. Poll NVMEN in the PDI Status Register (PDI STATUS) until NVMEN is set.
NVM commands available for external programming
Figure 30-4 on page
Table
30-5. This is a super-set of the commands available for self-
through
380.
Section 30.12.3.11 on page 385
Trigger
-
CMDEX
PDI Read
Change
Protected
explains in detail the
Y
N
-
XMEGA A
NVM Busy
Y
N
-
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