SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 150

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 20-2.
20.3.3.2
150
Symbol
FL_ID
FL_SIZE
FL_PAGE_SIZE
FL_NB_PLANE
FL_PLANE[0]
...
FL_PLANE[FL_NB_PLANE-1]
FL_NB_LOCK
FL_LOCK[0]
...
AT91SAM9XE128/256/512 Preliminary
Write Commands
Flash Descriptor Definition
ations to the EEFC_FRR register are done after the last word of the descriptor has been
returned, then the EEFC_FRR register value is 0 until the next valid command.
Several commands can be used to program the Flash.
Flash technology requires that an erase is done before programming. The full memory plane can
be erased at the same time, or several pages can be erased at the same time (refer to
Commands” on page
using EWP or EWPL commands.
After programming, the page (the whole lock region) can be locked to prevent miscellaneous
write or erase sequences. The lock bit can be automatically set after page programming using
WPL or EWPL commands.
Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds
to the page size. The latch buffer wraps around within the internal memory area address space
and is repeated as many times as the number of pages within this address space.
Note:
Write operations are performed in a number of wait states equal to the number of wait states for
read operations.
Data are written to the latch buffer before the programming command is written to the Flash
Command Register EEFC_FCR. The sequence is as follows:
Two errors can be detected in the EEFC_FSR register after a programming sequence:
• Write the full page, at any page address, within the internal memory area address space.
• Programming starts as soon as the page number and the programming command are written
• When programming is completed, the bit FRDY in the Flash Programming Status Register
to the Flash Command Register. The FRDY bit in the Flash Programming Status Register
(EEFC_FSR) is automatically cleared.
(EEFC_FSR) rises. If an interrupt has been enabled by setting the bit FRDY in EEFC_FMR,
the interrupt line of the System Controller is activated.
Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.
Word Index
0
1
2
3
4
4 + FL_NB_PLANE - 1
4 + FL_NB_PLANE
4 + FL_NB_PLANE + 1
151). Also, a page erase can be automatically done before a page write
Number of bytes in the first lock region.
Description
Flash Interface Description
Flash size in bytes
Page size in bytes
Number of planes.
Number of bytes in the first plane.
Number of bytes in the last plane.
Number of lock bits. A bit is associated
with a lock region. A lock bit is used to
prevent write or erase operations in the
lock region.
6254C–ATARM–22-Jan-10
“Erase