SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 26

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1.6.2
8.2
8.2.1
8.2.2
26
External Memories
AT91SAM9XE128/256/512 Preliminary
External Bus Interface
Static Memory Controller
GPNVMBit[3] = 1, Boot on Internal Flash
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz, the user must take the following steps:
The external memories are accessed through the External Bus Interface. Each Chip Select line
has a 256-Mbyte memory area assigned.
Refer to the memory map in
• Boot on slow clock (On-chip RC oscillator or 32,768 Hz low-power oscillator)
1. Program the PMC (main oscillator enable or bypass mode)
2. Program and start the PLL
3. Switch the main clock to the new value.
• Integrates three External Memory Controllers:
• Additional logic for NANDFlash
• Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64 Mbytes linear)
• Up to 8 chip selects, Configurable Assignment:
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
• Multiple device adaptability
• Multiple Wait State Management
• Slow Clock mode supported
– Static Memory Controller
– SDRAM Controller
– ECC Controller
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
– Static Memory Controller on NCS6-NCS7
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
Figure 8-1 on page
20.
6254C–ATARM–22-Jan-10