SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 455

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 33-8. Master Write with One Byte Internal Address and Multiple Data Bytes
33.7.5
455
TXCOMP
TXRDY
TWCK
TWD
Write THR (Data n)
AT91SAM9XE128/256/512 Preliminary
S
Master Receiver Mode
DADR
W
TXRDY is used as Transmit Ready for the PDC transmit channel.
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
Figure 33-9. Master Read with One Data Byte
A
IADR
TXCOMP
RXRDY
TWD
A
Figure
DATA n
S
Write START &
33-10. For Internal Address usage see
STOP Bit
DADR
A
Write THR (Data n+1)
R
Figure
A
33-9. When a multiple data byte read is
DATA n+1
DATA
STOP command performed
(by writing in the TWI_CR)
Write THR (Data n+2)
Last data sent
Read RHR
A
Section
N
Figure
DATA n+2
P
6254C–ATARM–22-Jan-10
33.7.6.
33-9. When the
A
P