SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 247

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

24.5.4
Figure 24-5. Refresh Cycle Followed by a Read Access
24.5.5
6254C–ATARM–22-Jan-10
SDRAMC_A[12:0]
D[31:0]
SDWE
(input)
SDCS
SDCK
RAS
CAS
SDRAM Controller Refresh Cycles
Power Management
Row n
col c col d
Dnb
Dnc
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is
loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles
between refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform.
It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the
device is busy and the master is held by a wait signal. See
Three low-power modes are available:
The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not
selected. It is possible to delay the entry in self-refresh and power-down mode after the last
access by programming a timeout value in the Low Power Register.
Dnd
• Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the
• Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between
• Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are
SDRAM Controller. Current drained by the SDRAM is very low.
auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is
higher than in Self-refresh Mode.
lost, but the SDRAM does not drain any current.
t
RP
= 3
AT91SAM9XE128/256/512 Preliminary
t
RC
= 8
Figure
Row m
24-5.
t
RCD
= 3
col a
CAS = 2
Dma
247