AD6643 Analog Devices, AD6643 Datasheet - Page 21

• Manufacturer Part Number: AD6643
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Data Sheet
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6643.
The full-scale input range can be adjusted by varying the reference
voltage via the SPI. The input span of the ADC tracks reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD6643 sample clock
inputs (CLK+ and CLK−) by using a differential signal. The
signal is typically ac-coupled into the CLK+ and CLK− pins via
a transformer or capacitors. These pins are biased internally
(see Figure 32) and require no external bias. If the inputs are
floated, the CLK− pin is pulled low to prevent spurious clocking.
Clock Input Options
The AD6643 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 33 and Figure 34 show two preferred methods for clocking
the AD6643 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD6643 to approximately 0.8 V p-p
differential. This limit helps prevent the large voltage swings of the
CLK+
Figure 32. Equivalent Clock Input Circuit
4pF
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
CENTERED AT 140MHz.
AD8376
AVDD
0.9V
1µH
1µH
Figure 31. Differential Input Configuration Using the AD8376
1nF
1000pF
1000pF
4pF
VPOS
CLK–
301Ω
180nH
180nH
Rev. A | Page 21 of 36
5.1pF
220nH
220nH
3.9pF
165Ω
165Ω
clock from feeding through to other portions of the AD6643, yet
preserves the fast rise and fall times of the signal, which are critical
to low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 35. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516, AD9517, AD9518, AD9520,
AD9522, and the ADCLK905/ADCLK907/ADCLK925, clock
drivers offer excellent jitter performance.
CLOCK
CLOCK
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 36. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516,
AD9517, AD9518, AD9520, AD9522, AD9523, and
clock drivers offer excellent jitter performance.
INPUT
INPUT
CLOCK
INPUT
CLOCK
INPUT
Figure 33. Transformer-Coupled Differential Clock (Up to 200 MHz)
50kΩ
1nF
Figure 34. Balun-Coupled Differential Clock (Up to 625 MHz)
Figure 35. Differential PECL Sample Clock (Up to 625 MHz)
15pF
VCM
50Ω
390pF
390pF
0.1µF
0.1µF
50kΩ
100Ω
68nH
ADT1-1WT, 1:1Z
AD95xx
PECL DRIVER
Mini-Circuits
XFMR
25Ω
25Ω
2.5kΩ║2pF
AD6643
240Ω
®
390pF
390pF
390pF
390pF
SCHOTTKY
HSMS2822
SCHOTTKY
HSMS2822
DIODES:
DIODES:
240Ω
0.1µF
0.1µF
100Ω
CLK+
CLK–
CLK+
CLK–
ADC
CLK+
CLK–
AD6643
AD9524
ADC
ADC