AD6643 Analog Devices, AD6643 Datasheet - Page 9

• Manufacturer Part Number: AD6643
• Description: Dual IF Receiver
• Manufacturer: Analog Devices

Data Sheet
Timing Diagrams
PARALLEL INTERLEAVED
CHANNEL MULTIPLEXED
CHANNEL MULTIPLEXED
(ODD/EVEN) MODE
(ODD/EVEN) MODE
CHANNEL A AND
Figure 2. LVDS Modes for Data Output Timing Latency. NSR Disabled (Enabling NSR Adds an Additional Three Clock Cycles of Latency)
CHANNEL B
CHANNEL A
CHANNEL B
DCO–
DCO+
CLK+
CLK–
D9/D10±
D9/D10±
VIN
(MSB)
0/D0±
(MSB)
0/D0±
(MSB)
(LSB)
(LSB)
(LSB)
D11
.
.
.
.
.
.
.
.
.
D0
SYNC
CLK+
N – 1
t
CH
t
SSYNC
t
A
Figure 3. SYNC Timing Inputs
t
t
PD
DCO
N
Rev. A | Page 9 of 36
N – 10
N – 10
N – 10
CH A9
N – 10
N – 10
CH B9
N – 10
CH A
CH A
t
CLK
0
0
t
SKEW
t
HSYNC
CH A10
CH B10
N – 10
N – 10
CH A0
N – 10
N – 10
CH B0
N – 10
N – 10
CH B
CH B
N + 1
CH A9
CH B9
CH A
N – 9
CH A
N – 9
N – 9
N – 9
N – 9
N – 9
0
0
CH A10
CH B10
CH A0
CH B0
CH B
N – 9
CH B
N – 9
N – 9
N – 9
N – 9
N – 9
N + 2
CH A9
CH B9
CH A
N – 8
CH A
N – 8
N – 8
N – 8
N – 8
N – 8
0
0
CH A10
CH B10
CH A0
CH B0
N + 3
CH B
N – 8
CH B
N – 8
N – 8
N – 8
N – 8
N – 8
CH A9
CH B9
CH A
N – 7
CH A
N – 7
N – 7
N – 7
N – 7
N – 7
0
0
CH A10
CH B10
CH A0
CH B0
N + 4
CH B
CH B
N – 7
N – 7
N – 7
N – 7
N – 7
N – 7
CH A9
CH B9
CH A
N – 6
CH A
N – 6
N – 6
N – 6
N – 6
N – 6
AD6643
0
0
N + 5