AD9641

Manufacturer Part NumberAD9641
Description14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
ManufacturerAnalog Devices
AD9641 datasheet
 


Specifications of AD9641

Resolution (bits)14bit# Chan1
Sample Rate80MSPSInterfaceSer
Analog Input TypeDiff-BipAin Range1.75 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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Data Sheet
FEATURES
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz/80 MSPS
SNR = 72.8 dBFS at 70 MHz and 155 MSPS
SFDR = 94 dBc at 70 MHz and 80 MSPS
SFDR = 90 dBc at 70 MHz and 155 MSPS
Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer (DCS)
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
GENERAL DESCRIPTION
The
AD9641
is a 14-bit, 80 MSPS/155 MSPS analog-to-digital
converter (ADC) with a high speed serial output interface. The
AD9641
is designed to support communications applications
where high performance, combined with low cost, small size, and
versatility, is desired. The JESD204A high speed serial interface
reduces board routing requirements and lowers pin count
requirements for the receiving device.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth, differential sample-and-hold,
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases the design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
14-Bit, 80 MSPS/155 MSPS, 1.8 V
Serial Output Analog-to-Digital Converter (ADC)
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9641
VIN+
VIN–
VCM
REFERENCE
AGND
The ADC output data is routed directly to the JESD204A serial
output port. This output is at CML voltage levels. A CMOS or
LVDS synchronization input (DSYNC) is provided.
The flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
The
AD9641
the industrial temperature range of −40°C to +85°C.
This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1.
An on-chip PLL allows users to provide a single ADC
sampling clock. The PLL multiplies the ADC sampling clock
to produce the corresponding JESD204A data rate clock.
2.
The configurable JESD204A output block coded data rate
supports up to 1.6 Gbps.
3.
A proprietary differential input maintains excellent SNR
performance for input frequencies of up to 250 MHz.
4.
Operation is from a single 1.8 V power supply.
5.
The standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding), control-
ling the clock DCS, power-down, test modes, voltage
reference mode, and serial output configuration.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9641
SDIO SCLK CSB
DRVDD
SPI
PROGRAMMING DATA
ADC
DATA RATE
MULTIPLIER
DUTY CYCLE
STABILIZER
DIVIDE-BY-1
MULTICHIP
TO
SYNC
DIVIDE-BY-8
SYNC
PDWN
DRGND
Figure 1.
is available in a 32-lead LFCSP and is specified over
www.analog.com
©2010–2012 Analog Devices, Inc. All rights reserved.
DOUT+
DOUT–
DSYNC+
DSYNC–
CLK+
CLK–

AD9641 Summary of contents

  • Page 1

    ... Gray coding), control- ling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 AD9641 SDIO SCLK CSB DRVDD SPI PROGRAMMING DATA ADC ...

  • Page 2

    ... AD9641 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 ADC DC Specifications ............................................................... 3 ADC AC Specifications ............................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Specifications .................................................................. 7 Absolute Maximum Ratings ............................................................ 8 Thermal Characteristics .............................................................. 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 10 Equivalent Circuits ......................................................................... 16 Theory of Operation ...

  • Page 3

    ... Rev Page AD9641 AD9641-155 Typ Max Unit Bits Guaranteed ±2 ±11 mV −2 FSR ±0.55 LSB ±0.3 LSB ±1.2 LSB ±0.5 LSB ±2 ppm/°C ±35 ppm/°C 0.7 LSB rms 1.75 2.087 V p kΩ ...

  • Page 4

    ... AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. 2 The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is 250 MHz. AD9641-80 Temperature Min ...

  • Page 5

    ... CMOS Full 1.22 Full 0 Full −10 Full 40 Full 26 Full 2 CMOS Full 1.22 Full 0 Full −92 Full −10 Full 26 Full 2 Rev Page AD9641 Max Unit V 3.6 V p-p AVDD V 1.4 V +100 μA +100 μ kΩ V AVDD V AVDD V 0.6 V +100 μA +100 μ kΩ ...

  • Page 6

    ... Rev Page Data Sheet Typ Max Unit CMOS 2.1 V 0.6 V +10 μA 128 μA 26 kΩ CML 0.8 1.1 V DRVDD/2 1.05 V AD9641-155 Min Typ Max Unit 640 MHz 40 155 MSPS 6.45 ns 1.935 3.225 4.515 ns 3.065 3.225 3.385 ns 0.8 ns 0.78 ns 0.125 ps rms 1/(20 × sec ...

  • Page 7

    ... ENCODED INTO 2 ENCODED INTO 2 8b/10b SYMBOLS 8b/10b SYMBOLS Figure 2. Data Output Timing t t SSYNC HSYNC Figure 3. SYNC Input Timing Requirements Rev Page AD9641 Limit 0.30 ns typ 0.30 ns typ 2 ns min 2 ns min 40 ns min 2 ns min 2 ns min 10 ns min 10 ns min ...

  • Page 8

    ... AD9641 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter ELECTRICAL AVDD to AGND DRVDD to AGND VIN+, VIN− to AGND CLK+, CLK− to AGND SYNC to AGND VCM to AGND CSB to AGND SCLK to AGND SDIO to AGND PDWN to AGND DOUT+, DOUT− to AGND DSYNC+, DSYNC− to AGND ENVIRONMENTAL Operating Temperature Range ...

  • Page 9

    ... CML Output Data—Complement. Input SPI Serial Clock. Input/output SPI Serial Data I/O. Input SPI Chip Select (Active Low). Input Power-Down Input. Using the SPI interface, this input can be configured as power-down or standby. Rev Page PDWN 23 DNC 22 CSB 21 SCLK 20 SDIO 19 DRVDD 18 DRVDD 17 DRGND AD9641 ...

  • Page 10

    ... MHz Figure 8. AD9641-80 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 30.1 MHz Figure 9. AD9641-80 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 Figure 10. AD9641-80 Single-Tone FFT with f = 70.1 MHz IN Rev Page Data Sheet 80MSPS 140.3MHz @ – ...

  • Page 11

    ... Figure 14. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency ( –20 –40 –60 –80 –100 –120 –90 ) Figure 15. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude ( –20 –40 –60 –80 –100 –120 200 250 –90 ) and Figure 16. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude ( MSPS S Rev ...

  • Page 12

    ... Figure 18. AD9641-80 Two-Tone FFT with 172.1 MHz IN2 100 SFDR SNR SAMPLE RATE (MSPS) Figure 19. AD9641-80 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 70.1 MHz IN 14,000 12,000 10,000 8000 6000 4000 2000 32.9 MHz IN2 –0.2 –0.4 –0.6 –0.8 – ...

  • Page 13

    ... MHz Figure 26. AD9641-155 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 0 = 30.1 MHz Figure 27. AD9641-155 Single-Tone FFT with –20 –40 –60 –80 –100 –120 –140 0 = 70.1 MHz Figure 28. AD9641-155 Single-Tone FFT with f IN Rev Page 155MSPS 140.1MHz @ – ...

  • Page 14

    ... Temperature with 1.75 V p-p Full Scale, f –30 –20 – Figure 32. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (f IN –30 –20 –10 0 Figure 33. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 200 250 300 ) and Figure 34. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude ( 155 MSPS S Rev Page 100 ...

  • Page 15

    ... Figure 36. AD9641-155 Two-Tone FFT with 172.1 MHz IN2 105 SFDR 100 SNR 110 SAMPLE RATE (MSPS) Figure 37. AD9641-155 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 70.1 MHz IN 6000 5000 4000 3000 2000 1000 = 32.9 MHz IN2 1.0 0.8 0.6 0.4 0.2 –0.2 –0.4 –0.6 –0.8 – ...

  • Page 16

    ... AD9641 EQUIVALENT CIRCUITS AVDD VIN Figure 41. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 42. Equivalent Clock Input Circuit DRVDD 4mA 4mA R TERM V DOUT+ CM 4mA 4mA Figure 43. Digital CML Output DRVDD 350Ω SDIO 30kΩ Figure 44. Equivalent SDIO Circuit AVDD CLK– ...

  • Page 17

    ... ADC. Rev Page AN-742 Application Note, Frequency Domain AN-827 Application BIAS PAR2 PAR2 S BIAS Figure 48. Switched-Capacitor Input AD9641 are not internally dc biased. AD9641 ADA4938-2 differential drivers provide AD9641 ...

  • Page 18

    ... At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve 15Ω the true SNR performance of the AD9641. For applications where VIN– AVDD SNR is a key parameter, differential double balun coupling is the ADC recommended input configuration (see Figure 51) ...

  • Page 19

    ... Data Sheet VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9641. The input full-scale range can be adjusted through the SPI port by adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be used to change the full-scale value between 1.383 V p-p and 2 ...

  • Page 20

    ... The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9641. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...

  • Page 21

    ... The JESD204A block for the configurations described in Table 10. JESD204A Link Settings N’ N/A SCR = Rev Page AD9641 digital output complies with the JEDEC Standard AD9641 is designed to support the Comments Maximum sample rate = 80 or 155 MSPS ...

  • Page 22

    ... AD9641 Figure 61 shows a simplified block diagram of the JESD204A link for the AD9641. The 8b/10b encoding works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. By default in the AD9641, the 14-bit converter word is broken into two octets. Bit 13 through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 and two tail bits ...

  • Page 23

    ... DRVDD/2; otherwise, ac coupling capacitors can be used to terminate to any single- ended voltage. The AD9641 begins the initial FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 Ω termination resistor placed as close as possible to the receiver logic ...

  • Page 24

    ... UIS: 8000; 1239996, TOTAL: 48000; 7439996 –600 –300 –200 –100 100 200 0 TIME (ps) Figure 68. AD9641-155 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations Table 12. Digital Output Coding Code (VIN+) − (VIN−), Input Span = 1.75 V p-p (V) 8191 +0.875 0 0.00 −1 − ...

  • Page 25

    ... A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9641. Various output test options are also provided to place predictable values on the outputs of the AD9641. ...

  • Page 26

    ... A description of the PN sequence long and how it is generated can be found in Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 13 for the initial values) and that the AD9641 standard. Table 13. PN Sequence Sequence PN Sequence Short ...

  • Page 27

    ... For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. t HIGH t CLK t LOW A12 A11 A10 Figure 70. Serial Port Interface Timing Diagram Rev Page DON’T CARE DON’T CARE AD9641 ...

  • Page 28

    ... The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9641. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...

  • Page 29

    ... ID[7:0] (AD9641 = 0x80) (default) Speed grade ID Open Open MSPS 10 = 155 MSPS Open Open Open Open Rev Page AD9641 is reset, critical registers are loaded with Default Default Bit 0 Value Notes/ Bit 1 (LSB) (Hex) Comments LSB first 0 0x18 Nibbles are ...

  • Page 30

    ... AD9641 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) ADC Functions 0x08 Power Open Open modes 0x09 Global clock Open Open 0x0A PLL status PLL locked Open 0x0B Clock divide Open Open 0x0D Test mode User test Open mode control 0 = continuous/ repeat ...

  • Page 31

    ... PN sequence, long 100 = PN sequence, short 111 = ramp output 0x00 0x00 0x00 0x00 Open Serial lane 0x80 control 0 = one lane per link ( reserved AD9641 Default Notes/ Comments Bit 3 must be enabled if the ADC clock rate is <60 MHz. Read only. Read only. ...

  • Page 32

    ... Converter resolution (N) (read only) Open Total number of bits per sample (N’) (read only) Open Samples per converter per frame cycle (S) (read only) (always 1 for the AD9641) Open Number of control words per frame clock cycle per link (CF) (always 0 for the Serial Reserved Field 1 (RES1) ...

  • Page 33

    ... programmed, the ILAS repeats one time, and so on. See Register 0x60, Bits[3:2] to enable the ILAS and for a test mode to continuously enable the initial lane alignment sequence. JESD204A Device Identification (DID) Number (Address 0x64) Bits[7:0]—Serial Device Identification (DID) Number Rev Page AD9641 ...

  • Page 34

    ... Bits[6:5]—Open Bits[4:0]—Number of Control Words per Frame Clock Cycle per Converter Device (Link) (CF) Read only bits. Reads back 0x0 for the AD9641. JESD204A Serial Reserved Field 1 (Address 0x76) Bits[7:0]—Serial Reserved Field 1 (RES1) This read/write register is available for customer use. ...

  • Page 35

    ... Power and Ground Recommendations When connecting power to the AD9641 recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD), and use a separate supply for the digital outputs (DRVDD) ...

  • Page 36

    ... AD9641BCPZRL7-80 −40°C to +85°C AD9641BCPZ-155 −40°C to +85°C AD9641BCPZRL7-155 −40°C to +85°C AD9641-80KITZ AD9641-155KITZ RoHS Compliant Part. ©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.10 ...