AD9641 Analog Devices, AD9641 Datasheet - Page 20

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
Input Clock Divider
The
to divide the input clock by integer values between 1 and 8.
For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS)
is optional. For other divide ratios, such as 3, 5, 6, 7, and 8, the
DCS must be enabled for proper part operation.
The
SYNC input. Bit 1 and Bit 2 of Register 0x03A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. The
tolerance on the clock duty cycle to maintain dynamic
performance characteristics.
The
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9641. Noise and distortion performance are nearly flat for a
wide range of duty cycles with the DCS enabled.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
of less than 20 MHz, nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 μs to 5 μs is required after a dynamic clock frequency
increase or decrease before the DCS loop is relocked to the
input signal. During the time when the loop is not locked, the
DCS loop is bypassed, and internal device timing is dependent
on the duty cycle of the input clock signal. In such applications,
it may be appropriate to disable the DCS. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. For inputs near full scale, the degradation in
SNR from the low frequency SNR (SNR
frequency (f
AD9641
AD9641
AD9641
SNR
HF
= −10 log[(2π × f
INPUT
clock divider can be synchronized using the external
contains an input clock divider with the ability
contains a DCS that retimes the nonsampling
) due to jitter (t
INPUT
JRMS
AD9641
× t
) can be calculated by
JRMS
)
LF
2
) at a given input
+ 10
requires a tight
(

SNR
LF
/
10
)
]
Rev. B | Page 20 of 36
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 59. The measured curve
in Figure 59 was taken using an ADC clock source with approxi-
mately 65 f
inherent in the
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9641.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the
Note for more information about jitter performance as it relates
to ADCs.
CHIP SYNCHRONIZATION
The
synchronization options for synchronizing the clock divider.
The clock divider sync feature is useful for guaranteeing synchro-
nized sample clocks across multiple ADCs. The input clock
divider can be enabled to synchronize on a single occurrence of
the SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally syn-
chronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
AD9641
75
70
65
60
55
50
1
S
AN-501
of jitter, which combines with the 125 f
has a SYNC input that offers the user flexible
Figure 59. SNR vs. Input Frequency and Jitter
AD9641
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
Application Note and the
INPUT FREQUENCY (MHz)
10
to produce the result shown.
100
AN-756
Data Sheet
S
of jitter
Application
1000