AD9641 Analog Devices, AD9641 Datasheet - Page 34

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9641
JESD204A Bank Identification (BID) Number (Address 0x65)
Bits[7:4]—Open
Bits[3:0]—Serial Bank Identification (BID) Number
JESD204A Lane Identification (LID) Number (Address 0x66)
Bits[7:5]—Open
Bits[4:0]—Serial Lane Identification (LID) Number for
Lane
JESD204A Scrambler (SCR) and Lane (L) Configuration
(Address 0x6E)
Bit 7—Enable Serial Scrambler Mode (SCR)
Setting this bit high enables the scrambler (SCR = 1).
Bits[6:1]—Open.
Bit 0—Serial Lane Control.
0: one lane per link (L = 1).
1: 11111 = reserved.
JESD204A Number of Octets per Frame (Address 0x6F,
Read Only)
Bits[7:0]—Number of Octets per Frame (F)
The readback from this register is calculated from the following
equation: F = (M × 2)/L.
Valid values for F for the
F = 2, with M = 1 and L = 1
JESD204A Number of Frames per Multiframe (K)
(Address 0x70)
Bits[7:5]—Open
Bits[4:0]—Number of Frames per Multiframe (K)
JESD204A Number of Converters per Converter Device
(Link) (M) (Address 0x71)
Bits[7:1]—Open
Bit 0—Number of Converters per Converter Device (Link)
(M)
0: link connected to one ADC. Only primary input used (M = 1).
1: reserved.
JESD204A Converter Resolution (N) and Control Bits per
Sample (CS) (Address 0x72)
Bits[7:6]—Number of Control Bits per Sample (CS)
00: no control bits sent per sample (CS = 0).
01: one control bit sent per sample—overrange bit enabled
(CS = 1).
10: two control bits sent per sample—overflow/underflow bits
enabled (CS = 2).
11: unused.
AD9641
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Bit 5—Open
Bits [4:0]—Converter Resolution (N).
Read only bits showing the converter resolution (reads back 13
(0xD) for 14-bit resolution).
JESD204A Total Number of Bits per Sample (N’)
(Address 0x73)
Bits[7:5]—Reserved
Bits[4:0]—Total Number of Bits per Sample (N’)
Read only bits showing the total number of bits per sample,
minus 1 (reads back 15 (0xF) for 16 bits per sample).
JESD204A Samples per Converter per Frame Cycle (S)
(Address 0x74)
Bits[7:5]—Open
Bits[4:0]—Samples per Converter per Frame Cycle (S)
Read only bits showing the number of samples per converter
frame cycle, minus 1 (reads back 0 (0x0) for one sample per
converter frame).
JESD204A HD and CF Configuration (Address 0x75)
Bit 7—High Density Format Enabled (Read Only)
Read only bit. Always 0 in the AD9641.
Bits[6:5]—Open
Bits[4:0]—Number of Control Words per Frame Clock
Cycle per Converter Device (Link) (CF)
Read only bits. Reads back 0x0 for the AD9641.
JESD204A Serial Reserved Field 1 (Address 0x76)
Bits[7:0]—Serial Reserved Field 1 (RES1)
This read/write register is available for customer use.
JESD204A Serial Reserved Field 2 (Address 0x77)
Bits[7:0]—Serial Reserved Field 2 (RES2)
This read/write register is available for customer use.
JESD204A Serial Checksum Value for Lane (Address 0x78)
Bits[7:0]—Checksum Value for Lane
This read only register is automatically calculated for the lane.
Sum (all link configuration parameters for the lane) MOD 256.
Data Sheet