ADP5065 Analog Devices, ADP5065 Datasheet - Page 33

• Manufacturer Part Number: ADP5065
• Description: Fast Charge Battery Management with Power Path and USB Compatibility
• Manufacturer: Analog Devices

Specifications of ADP5065

• Product Description: Fast Charge Battery Management with Power Path and USB Compatibility
• Switching/linear: Switching
• Cell Type: Li-Ion
• Final Voltage Options: 4.2
• Accuracy Over Temp (%): 0.3%
• Temp Range: -40 to +125°C
• Package: WLCSP-20
• Active For Param Search: Yes

Data Sheet
APPLICATIONS INFORMATION
EXTERNAL COMPONENTS
Inductor Selection
The high switching frequency of the
allows for the selection of small chip inductors. Suggested
inductors are shown in Table 33.
The peak-to-peak inductor current ripple is calculated using
the following equation:
where:
V
V
f
L is the inductor value.
The minimum dc current rating of the inductor must be greater
than the inductor peak current. The inductor peak current is
calculated using the following equation:
Inductor conduction losses are caused by the flow of current
through the inductor, which has an associated internal dc
resistance (DCR). Larger sized inductors have smaller DCR,
which may decrease inductor conduction losses. Inductor core
losses are related to the magnetic permeability of the core material.
Because the bucks are high switching frequency dc-to-dc
converters, shielded ferrite core material is recommended for
its low core losses and low EMI.
ISO_Sx (V
To safely obtain stable operation of the ADP5065, the ISO_Sx
and ISO_Bx effective capacitance (including temperature and
dc bias effects) must not be less than 10 μF at any point during
operation. The combined effective capacitance of the ISO_Sx
capacitor and the system capacitance must not exceed 50 μF at
any point during operation.
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
output voltage dc bias.
Ceramic capacitors are manufactured with a variety of dielec-
trics, each with a different behavior over temperature and
applied voltage. Capacitors must have a dielectric adequate
enough to ensure the minimum capacitance over the necessary
temperature range and dc bias conditions. X5R or X7R dielectrics
with a voltage rating of 6.3 V or 10 V are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor temper-
ature and dc bias characteristics.
SW
OUT
IN
is the switching frequency.
is the converter input voltage at the CFILT node.
I
is the ISO_Sx node output voltage.
I
RIPPLE
PEAK
OUT
=
=
I
) and ISO_Bx Capacitor Selection
V
CHG
OUT
V
+
IN
×
I
(
LOAD
×
V
f
IN
SW
(
−
MAX
×
V
L
OUT
)
+
)
I
RIPPLE
2
ADP5065
buck converter
Rev. A | Page 33 of 40
The worst-case capacitance accounting for capacitor variation
over temperature, component tolerance, and voltage is calcu-
lated using the following equation:
where:
C
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient
(TEMPCO) over −40°C to +85°C is assumed to be 15% for an
X5R dielectric. The tolerance of the capacitor (TOL) is assumed
to be 10%, and C
Substituting these values in the equation yields
To guarantee the performance of the charger in various
operation modes including trickle charge, constant current
charge, and constant voltage charge, it is imperative that the
effects of dc bias, temperature, and tolerances on the behavior
of the capacitors be evaluated for each application.
The peak-to-peak output voltage ripple for the selected output
capacitor and inductor values is calculated using the following
equation:
Capacitors with lower effective series resistance (ESR) are
preferable to guarantee low output voltage ripple, as shown in
the following equation:
EFF
is the effective capacitance at the operating voltage.
C
C
V
ESR
EFF
EFF
RIPPLE
Figure 39. Murata GRM31CR60J226ME19C DC Characteristic
25
20
15
10
5
0
= C
= 16 μF × (1 − 0.15) × (1 − 0.1) ≈ 12.24 μF
COUT
0
=
OUT
≤
8
×
× (1 − TEMPCO) × (1 − TOL)
V
1
I
OUT
RIPPLE
f
RIPPLE
I
SW
RIPPLE
is 16 μF at 4.2 V, as shown in Figure 39.
×
2
C
OUT
DC BIAS (V)
≈
3
(
2
π
×
4
f
SW
V
)
2
IN
×
5
L
×
C
OUT
ADP5065
6
7