ADP5065 Analog Devices, ADP5065 Datasheet - Page 6

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ADP5065

Manufacturer Part Number
ADP5065
Description
Fast Charge Battery Management with Power Path and USB Compatibility
Manufacturer
Analog Devices
Datasheet

Specifications of ADP5065

Product Description
Fast Charge Battery Management with Power Path and USB Compatibility
Switching/linear
Switching
Cell Type
Li-Ion
Final Voltage Options
4.2
Accuracy Over Temp (%)
0.3%
Temp Range
-40 to +125°C
Package
WLCSP-20
Active For Param Search
Yes
ADP5065
I
Table 3.
Parameter
I
1
2
Timing Diagram
2
2
Guaranteed by design.
A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See
diagram.
C-COMPATIBLE INTERFACE
C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Capacitive Load, Each Bus Line
SCL Clock Frequency
SCL High Time
SCL Low Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Hold Time for Start/Repeated Start
Bus Free Time Between a Stop and a Start Condition
Setup Time for Stop Condition
Rise Time of SCL/SDA
Fall Time of SCL/SDA
Pulse Width of Suppressed Spike
1
SDA
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
SCL
S
2
t
LOW
t
R
t
HD,DAT
t
SU,DAT
t
HIGH
Figure 2. I
Rev. A | Page 6 of 40
t
2
F
C Timing Diagram
t
F
Sr
t
SU,STA
Symbol
C
f
t
t
t
t
t
t
t
t
t
t
t
t
HD,STA
SCL
HIGH
LOW
SUDAT
HDDAT
SUSTA
HDSTA
BUF
SUSTO
R
F
SP
S
t
t
SU,STO
Min
0.6
1.3
100
0
0.6
0.6
1.3
0.6
20
20
0
SP
t
R
Typ
P
t
BUF
Figure 2
S
300
Max
400
400
0.9
300
50
Data Sheet
, the I
2
C timing
Unit
pF
kHz
μs
μs
ns
μs
μs
μs
μs
μs
ns
ns
ns

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