ADP5065 Analog Devices, ADP5065 Datasheet - Page 35

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ADP5065

Manufacturer Part Number
ADP5065
Description
Fast Charge Battery Management with Power Path and USB Compatibility
Manufacturer
Analog Devices
Datasheet

Specifications of ADP5065

Product Description
Fast Charge Battery Management with Power Path and USB Compatibility
Switching/linear
Switching
Cell Type
Li-Ion
Final Voltage Options
4.2
Accuracy Over Temp (%)
0.3%
Temp Range
-40 to +125°C
Package
WLCSP-20
Active For Param Search
Yes
Data Sheet
PCB LAYOUT GUIDELINES
Poor layout can affect
magnetic interference (EMI) and electromagnetic compatibility
(EMC) problems, ground bounce, and voltage losses. Poor
layout can also affect regulation and stability. A good layout is
implemented using the following guidelines:
Place the inductor, input capacitor, and output capacitor
close to the IC using short tracks. These components carry
high switching frequencies, and large tracks act as antennas.
TO MCU/NC
TO MCU/NC
ADP5065
TO MCU
TO MCU
(OPTIONAL)
1.5kΩ
R3/NC
R1
performance, causing electro-
VIN = 4.5V TO 5.5V
1.5kΩ
VDDIO
R2
E2
A2
B1
A4
B2
A1
CFILT
SCL
SDA
IIN_EXT
TRK_EXT
V_WEAK_SET
VIN1
D1
E1
BATTERY ISOLATION)
CHARGE CONTROL
Figure 40. Reference Circuit Diagram
C2
(INPUT CURRENT,
VIN2
(CHARGE MODE,
CONTROL
DC-DC)
Rev. A | Page 35 of 40
D4
ADP5065
E4
SYS_ON_OK
BAT_SNS
ISO_B1
ISO_B2
ISO_S1
ISO_S2
Route the output voltage path away from both the inductor
and SWxnode to minimize noise and magnetic interference.
Maximize the size of ground metal on the component side
to help with thermal dissipation.
Use a ground plane with several vias connecting to the
component side ground to further reduce noise
interference on sensitive circuit nodes.
SW1
SW2
THR
D3
E3
C3
C4
B3
B4
C1
A3
D2
10kΩ
LQH32PN1R0NN0
R4
VDDIO
L1 1µH
CLOSE TO
CONNECT
BATTERY
TO MCU
+
ADP5065

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