ADP5042

Manufacturer Part NumberADP5042
DescriptionMicro PMU with 0.8 A Buck, Two 300 mA LDOs, Supervisory, Watchdog and Manual Reset
ManufacturerAnalog Devices
ADP5042 datasheet
 


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ADP5042
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Preliminary Pin Function Descriptions
Pin No.
Mnemonic
Description
1
NC
Do not connect to this pin.
2
VOUT3
LDO2 Output Voltage and Sensing Input.
3
VIN3
LDO2 Input Supply (1.7 V to 5.5 V).
4
EN3
Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2.
5
nRSTO
Open-Drain Reset Output, Active Low.
6
AVIN
Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V).
7
VIN1
Buck Input Supply (2.3 V to 5.5 V).
8
SW
Buck Switching Node.
9
PGND
Dedicated Power Ground for Buck Regulator.
10
EN1
Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck.
11
VOUT1
Buck Sensing Node.
12
WDI2
Watchdog 2 (Long Timeout) Refresh Input from Processor. Can be disabled only by factory option.
13
VIN2
LDO1 Input Supply (1.7 V to 5.5 V).
14
VOUT2
LDO1 Output Voltage and Sensing Input.
15
WSTAT
Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low:
Watchdog 2 timeout. Auto cleared after one second.
16
EN2
Enable LDO1. EN2 = high: turn on LDO1. EN2 = low: turn off LDO1.
17
MODE
Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: buck regulator operates
in pulse skipping mode (PSM) at light load and in constant PWM at higher load.
18
WMOD
Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by
a three-state condition applied on WDI1.
19
WDI1
Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled.
20
Manual Reset Input, Active Low.
MR
TP
AGND
Analog Ground (TP = Thermal Pad). Exposed pad should be connected to AGND.
15 WSTAT
NC
1
VOUT3
2
14
VOUT2
ADP5042
VIN3
3
13
VIN2
TOP VIEW
EN3
4
12
WDI2
(Not to Scale)
nRSTO
5
11 VOUT1
NOTES
1. EXPOSED PAD SHOULD BE CONNECTED TO AGND.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 2. Pin Configuration—View from Top of the Die
Rev. A | Page 8 of 32
Data Sheet