P89LPC933_934_935_936 NXP Semiconductors, P89LPC933_934_935_936 Datasheet
P89LPC933_934_935_936
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P89LPC933_934_935_936 Summary of contents
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P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB/ byte-erasable flash with 8-bit ADCs Rev. 8 — 12 January 2011 1. General description The P89LPC933/934/935/936 is a single-chip microcontroller, available in low cost packages, based ...
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... Four interrupt priority levels. Eight keypad interrupt inputs, plus two additional external interrupt inputs. Schmitt trigger port inputs. Second data pointer. Emulation support. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. ...
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... Type number P89LPC933HDH P89LPC933FDH P89LPC935FA P89LPC934FDH P89LPC935FDH P89LPC935FHN P89LPC936FDH P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core highlights the differences between the four devices. For a complete list of device Section 2 “Features and Product comparison overview Flash memory Sector size 4 kB ...
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... NXP Semiconductors 5. Block diagram P89LPC933/934/935/936 P3[1:0] P2[7:0] P1[7:0] P0[7:0] X1 CRYSTAL OR RESONATOR X2 Fig 1. Block diagram P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ACCELERATED 2-CLOCK 80C51 CPU 4 kb/8 kB/16 kB CODE FLASH internal bus 256-BYTE DATA RAM 512-BYTE AUXILIARY RAM 512-BYTE DATA EEPROM (P89LPC935/936) PORT 3 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core P2.0/DAC0 1 2 P2.1 3 P0.0/CMP2/KBI0 4 P1.7 P1.6 5 P1.5/RST 6 P89LPC933HDH P89LPC933FDH 8 P3.1/XTAL1 P89LPC934FDH 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 12 P1.2/T0/SCL 13 P2.2/MOSI 14 P2.3/MISO P89LPC933/934 TSSOP28 pin configuration P2.0/ICB/DAC0/AD03 1 P2 ...
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... NXP Semiconductors Fig 4. Fig 5. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 5 P1.6/OCB P1.5/RST P3.1/XTAL1 8 P89LPC935FA 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 P89LPC935 PLCC28 pin configuration terminal 1 index area 1 P1.6/OCB 2 P1.5/RST P89LPC935FHN 4 P3.1/XTAL1 5 P3.0/XTAL2/CLKOUT 6 P1.4/INT1 7 P1.3/INT0/SDA Transparent top view P89LPC935 HVQFN28 pin configuration All information provided in this document is subject to legal disclaimers ...
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... KBI5 P0.6/CMP1 KBI6 P0.7/T1 KBI7 P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O Port 0: Port 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled ...
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... P1.6/OCB 5 1 P1.7/OCC AD00 P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Type Description [1] I/O, I Port 1: Port 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled ...
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... SPICLK P2.6/OCA 27 23 P2.7/ICA 28 24 P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O Port 2: Port 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled ...
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... [1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O Port 3: Port 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled ...
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... AD01 KBI1 AD10 KBI2 AD11 KBI3 AD12 DAC1 KBI4 AD13 KBI5 KBI6 KBI7 CLKOUT Fig 7. P89LPC935/936 logic symbol P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core V CMP2 CIN2B CIN2A CIN1B PORT 0 CIN1A CMPREF CMP1 T1 P89LPC933 P89LPC934 XTAL2 ...
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... reserved bit and may be used in future derivatives. – Logic 0 must be written with logic 0, and will return a logic 0 when read. – Logic 1 must be written with logic 1, and will return a logic 1 when read. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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Table 5. Special function registers - P89LPC933/934 * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON0 A/D control register 0 8EH ADCON1 A/D control register 1 97H ADINS A/D input select A3H ...
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Table 5. Special function registers - P89LPC933/934 * indicates SFRs that are bit addressable. Name Description SFR addr. FMADRL Program flash address low E6H FMCON Program flash control (Read) E4H Program flash control (Write) E4H FMDATA Program flash data E5H ...
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Table 5. Special function registers - P89LPC933/934 * indicates SFRs that are bit addressable. Name Description SFR addr. KBCON Keypad control register 94H KBMASK Keypad interrupt mask 86H register KBPATN Keypad pattern register 93H Bit address P0* Port 0 80H ...
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Table 5. Special function registers - P89LPC933/934 * indicates SFRs that are bit addressable. Name Description SFR addr. RTCH Real-time clock register high D2H RTCL Real-time clock register low D3H SADDR Serial port address register A9H SADEN Serial port address ...
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Table 5. Special function registers - P89LPC933/934 * indicates SFRs that are bit addressable. Name Description SFR addr. WDL Watchdog load C1H WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H [1] Unimplemented bits in SFRs (labeled ’-’) are ...
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Table 6. Special function registers - P89LPC935/936 * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H ADCON0 A/D control register 0 8EH ADCON1 A/D control register 1 97H ADINS A/D input select A3H ...
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Table 6. Special function registers - P89LPC935/936 * indicates SFRs that are bit addressable. Name Description SFR addr. CCCRB Capture compare B control EBH register CCCRC Capture compare C control ECH register CCCRD Capture compare D control EDH register CMP1 ...
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Table 6. Special function registers - P89LPC935/936 * indicates SFRs that are bit addressable. Name Description SFR addr. I2SCLL Serial clock generator/SCL DCH duty cycle register low 2 I2STAT I C status register D9H ICRAH Input capture A register high ...
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Table 6. Special function registers - P89LPC935/936 * indicates SFRs that are bit addressable. Name Description SFR addr. OCRCH Output compare C register FDH high OCRCL Output compare C register FCH low OCRDH Output compare D register FFH high OCRDL ...
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Table 6. Special function registers - P89LPC935/936 * indicates SFRs that are bit addressable. Name Description SFR addr. RSTSRC Reset source register DFH RTCCON Real-time clock control D1H RTCH Real-time clock register high D2H RTCL Real-time clock register low D3H ...
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Table 6. Special function registers - P89LPC935/936 * indicates SFRs that are bit addressable. Name Description SFR addr. TL2 CCU timer low CCH TMOD Timer 0 and 1 mode 89H TOR2H CCU reload register high CFH TOR2L CCU reload register ...
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... The P89LPC933/934/935/936 supports a user-selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core ⁄ ...
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... NXP Semiconductors XTAL1 XTAL2 (400 kHz +30 % −20 %) Fig 8. P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY RC RCCLK OSCILLATOR (7.3728 MHz ±1 %) WATCHDOG OSCILLATOR TIMER 0 AND 2 I TIMER 1 Block diagram of oscillator control All information provided in this document is subject to legal disclaimers. ...
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... Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip XDATA memory. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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... External interrupt inputs The P89LPC933/934/935/936 has two external interrupt inputs as well as the Keypad Interrupt function. The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Section 8.27 “Data EEPROM ...
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... BNDI1 EADEE (P89LPC935) EAD (P89LPC933/934) (1) See Section 8.19 “CCU (P89LPC935/936)” (2) P89LPC935/936 Fig 9. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Section 8.15 “Power reduction modes” IE0 EX0 IE1 EX1 ...
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... To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Number of I/O pins available ...
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... The P89LPC933/934/935/936 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Table 11 “ ...
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... Comparators (note that Comparators can be powered-down separately), and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core (see Table 11 “ ...
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... The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT. the device is forced into ISP mode during power-on (see P89LPC933/934/935/936 User manual). Otherwise, instructions will be fetched from address 0000H. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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... When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers ...
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... The capture event can be programmed to be either rising or falling edge triggered. A simple noise filter can be enabled on the input capture by enabling the Input P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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... However, since bit FCO is used to hold the halt value, only a compare event can change the state of the pin. Fig 10. Asymmetrical PWM, down-counting mode Fig 11. Symmetrical PWM P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... SFR register TCR21. The PLL frequency can be expressed as shown in PLL frequency Where the value of PLLDV.3 to PLLDV.0. Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... CPU 32 8.20.1 Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at frequency. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core other interrupt sources ...
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... Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is logic 0, SCON.7 is SM0 recommended that SM0 and SM1 (SCON.7:6) are set up when SMOD0 is logic 0. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core selection” ...
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... TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the Tx interrupt. If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core bit (bit 8) in double buffering (modes 1, 2 and 3) All information provided in this document is subject to legal disclaimers ...
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... Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer • The I A typical I device provides a byte-oriented I 400 kHz. Fig 15. I P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 2 C-bus may be used for test and diagnostic purposes. 2 C-bus configuration is shown in ...
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... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 16. I P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram All information provided in this document is subject to legal disclaimers. ...
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... SS is the optional slave select pin typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 8-BIT SHIFT REGISTER ...
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... NXP Semiconductors 8.22.1 Typical SPI configurations Fig 18. SPI single master single slave configuration Fig 19. SPI dual device configuration, where either can be a master or a slave P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI ...
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... NXP Semiconductors Fig 20. SPI single master multiple slaves configuration P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK port GENERATOR port All information provided in this document is subject to legal disclaimers. ...
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... Internal reference voltage An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred 1.23 V ± ref(bg) P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core = 2 ...
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... In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than six CCLKs. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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... Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 ...
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... Programmable security for the code in the flash for each sector. • 100,000 typical erase/program cycles for each byte. • 10 year minimum data retention. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. ...
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... PGM_MTP at FF03H. The boot ROM occupies the program memory space at the top of the address space from FF00H to FFEFH, thereby not conflicting with the user program memory space. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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... A custom boot loader can be written with the boot vector set to the custom boot loader, if desired. Table 9. Device P89LPC933 P89LPC934 P89LPC935 P89LPC936 P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core , V , TXD, RXD, and RST). Only a small connector needs shows the factory default boot vector settings for these devices. ...
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... Auto scan, continuous conversion mode. Dual channel, continuous conversion mode. Single step mode. Four conversion start modes: Timer triggered start. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — 12 January 2011 Figure 23 ...
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... A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel. An interrupt, if enabled, will be generated after the conversion completes. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... A/D operating modes. 9.5.2 Start immediately Programming this mode immediately starts a conversion. This start mode is available in all A/D operating modes. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. ...
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... Idle mode when the conversion is completed if the A/D interrupt is enabled. In Power-down mode or Total Power-down mode, the A/D does not function. If the A/D is enabled, it will consume power. Power can be reduced by disabling the A/D. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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... Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... V LOW-level output voltage OL V HIGH-level output voltage OH V crystal voltage xtal V voltage on any other pin n C input capacitance iss P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Conditions MHz DD osc MHz DD osc V = 3.6 V ...
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... Measured with port in high-impedance mode. [9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when V is approximately P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core …continued Conditions ...
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... 3.6 V; push-pull mode amb DD Fig 24 function P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core OH 002aab098 (typical values) OH All information provided in this document is subject to legal disclaimers. Rev. 8 — 12 January 2011 ...
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... SPI operating frequency SPI slave master T SPI cycle time SPICYC slave master t SPI enable lead time SPILEAD slave P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Conditions Min 7.189 320 see Figure 27 P1.5/RST pin any pin except P1.5/RST P1 ...
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... SPI inputs (SPICLK, MOSI, MISO, SS) [1] Parameters are valid over ambient temperature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core …continued Conditions ...
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... SPI cycle time SPICYC slave master t SPI enable lead time SPILEAD slave t SPI enable lag time SPILAG slave P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Conditions Min 7.189 320 see Figure 27 P1.5/RST pin any pin except P1 ...
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... SPI inputs (SPICLK, MOSI, MISO, SS) [1] Parameters are valid over ambient temperature range unless otherwise specified. [2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core …continued Conditions ...
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... SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 26. SPI master timing (CPHA = 0) Fig 27. External clock timing (with an amplitude of at least V P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core T XLXL t XHQX XHDX valid ...
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... SS t SPIF t SPILEAD SPICLK (CPOL = 0) (input) t SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 29. SPI slave timing (CPHA = 0) P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core T SPICYC t t SPIF SPIR t SPICLKL t SPICLKH t SPIF t SPICLKL t SPICLKH t t SPIDSU ...
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... T amb Symbol Parameter t RST delay from RST HIGH time RH t RST LOW time RL Fig 31. ISP entry timing P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core T SPICYC t t SPIF SPIR t SPICLKL t SPICLKH t SPIR t ...
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... I input leakage current LI [1] This parameter is characterized, but not tested in production. P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Conditions 0 < V < All information provided in this document is subject to legal disclaimers. ...
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... T ADC clock cycle time cy(ADC) t ADC conversion time ADC P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Conditions 0 kHz to 100 kHz A/D enabled All information provided in this document is subject to legal disclaimers. Rev. 8 — 12 January 2011 ...
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... Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION IEC SOT261-2 112E08 Fig 32. Package outline SOT261-2 (PLCC28) P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT361-1 Fig 33. Package outline SOT361-1 (TSSOP28) P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION IEC SOT788 Fig 34. Package outline SOT788-1 (HVQFN28) P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 2.5 scale ...
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... EMI LED PWM RAM RC RTC SAR SFR SPI UART P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core Acronym list Description Analog to Digital Central Processing Unit Digital to Analog Converter Erasable Programmable Read-Only Memory Electrically Erasable Programmable Read-Only Memory ...
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... Revision history Table 18. Revision history Document ID P89LPC933_934_ 935_936 v.8 Modifications: P89LPC933_934_ 935_936 v.7 P89LPC933_934_ 935_936 v.6 P89LPC933_934_ 935_936 v.5 P89LPC933_934_ 935 v.4 P89LPC933_934_935_936 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Release Data sheet status date 20110112 Product data sheet • Table 10 “Limiting values”: Changed V • ...
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... Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 18. Contact information For more information, please visit: For sales office addresses, please send an email to: P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Port 0 analog functions . . . . . . . . . . . . . . . . . . 31 8.13.3 Additional port features 8.14 Power monitoring functions . . . . . . . . . . . . . . 31 8.14.1 Brownout detection . . . . . . . . . . . . . . . . . . . . . 32 8.14.2 Power-on detection 8.15 Power reduction modes . . . . . . . . . . . . . . . . . 32 8.15.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.15.2 Power-down mode . . . . . . . . . . . . . . . . . . . . . 32 P89LPC933_934_935_936 Product data sheet P89LPC933/934/935/936 8-bit microcontroller with accelerated two-clock 80C51 core 8.15.3 Total Power-down mode . . . . . . . . . . . . . . . . 33 8.16 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.16.1 Reset vector 8.17 Timers/counters 0 and 8.17.1 Mode 8.17.2 Mode 1 ...
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... NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Contact information . . . . . . . . . . . . . . . . . . . . 75 Contents Date of release: 12 January 2011 Document identifier: P89LPC933_934_935_936 All rights reserved. ...