P89LPC933_934_935_936 NXP Semiconductors, P89LPC933_934_935_936 Datasheet - Page 38

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P89LPC933_934_935_936

Manufacturer Part Number
P89LPC933_934_935_936
Description
The P89LPC933/934/935/936 is a single-chip microcontroller, available in low costpackages, based on a high performance processor architecture that executes instructionsin two to four clocks, six times the rate of standard 80C51 devices
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
P89LPC933_934_935_936
Product data sheet
Fig 13. Capture/compare unit interrupts
TOCIE2C (TICR2.5)
TOCIE2D (TICR2.6)
TOCIE2A (TICR2.3)
TOCIE2B (TICR2.4)
TOCF2C (TIFR2.5)
TOCF2D (TIFR2.6)
TICIE2A (TICR2.0)
TICIE2B (TICR2.1)
TOCF2A (TIFR2.3)
TOCF2B (TIFR2.4)
TICF2A (TIFR2.0)
TICF2B (TIFR2.1)
8.19.9 CCU interrupts
8.20.1 Mode 0
TOIE2 (TICR2.7)
TOIF2 (TIFR2.7)
ECCU (IEN1.4)
8.20 UART
EA (IEN0.7)
There are seven interrupt sources on the CCU which share a common interrupt vector.
The P89LPC933/934/935/936 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate
source. The P89LPC933/934/935/936 does include an independent baud rate generator.
The baud rate can be selected from the oscillator (divided by a constant), Timer 1
overflow, or the independent baud rate generator. In addition to the baud rate generation,
enhancements over the standard 80C51 UART include Framing Error detection,
automatic address recognition, selectable double buffering and several interrupt options.
The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU
clock
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
frequency.
32
or CPU
clock
All information provided in this document is subject to legal disclaimers.
16
.
Rev. 8 — 12 January 2011
8-bit microcontroller with accelerated two-clock 80C51 core
ENCODER
PRIORITY
P89LPC933/934/935/936
interrupt
sources
other
1
16
of the CPU clock
002aaa896
interrupt to
CPU
ENCINT.0
ENCINT.1
ENCINT.2
© NXP B.V. 2011. All rights reserved.
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