P89LPC933_934_935_936 NXP Semiconductors, P89LPC933_934_935_936 Datasheet - Page 60

• Manufacturer Part Number: P89LPC933_934_935_936
• Description: The P89LPC933/934/935/936 is a single-chip microcontroller, available in low costpackages, based on a high performance processor architecture that executes instructionsin two to four clocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

NXP Semiconductors
12. Dynamic characteristics
Table 12.
V
T
P89LPC933_934_935_936
Product data sheet
Symbol
f
f
f
T
f
Glitch filter
t
t
External clock
t
t
t
t
Shift register (UART mode 0)
T
t
t
t
t
SPI interface
f
T
t
osc(RC)
osc(WD)
osc
CLKLP
gr
sa
CHCX
CLCX
CLCH
CHCL
QVXH
XHQX
XHDX
XHDV
SPI
SPILEAD
amb
DD
cy(clk)
XLXL
SPICYC
= 2.4 V to 3.6 V unless otherwise specified.
= −40 °C to +85 °C for industrial, −40 °C to +125 °C for extended, unless otherwise specified.
Dynamic characteristics (12 MHz)
Parameter
internal RC oscillator frequency
internal watchdog oscillator
frequency
oscillator frequency
clock cycle time
low-power select clock
frequency
glitch rejection time
signal acceptance time
clock HIGH time
clock LOW time
clock rise time
clock fall time
serial port clock cycle time
output data set-up to clock rising
edge time
output data hold after clock
rising edge time
input data hold after clock rising
edge time
input data valid to clock rising
edge time
SPI operating frequency
SPI cycle time
SPI enable lead time
slave
master
slave
master
slave
All information provided in this document is subject to legal disclaimers.
Conditions
see
P1.5/RST pin
any pin except
P1.5/RST
P1.5/RST pin
any pin except
P1.5/RST
see
see
see
see
see
see
see
see
see
see
29,
see
Rev. 8 — 12 January 2011
30
Figure 27
Figure 27
Figure 27
Figure 27
Figure 27
Figure 25
Figure 25
Figure 25
Figure 25
Figure 25
Figure
Figure
8-bit microcontroller with accelerated two-clock 80C51 core
26, 28,
29,
30
P89LPC933/934/935/936
16T
13T
6
4
7.189
⁄
⁄
Min
320
125
150
250
CCLK
CCLK
83
50
33
33
cy(CLK)
cy(CLK)
0
0
0
-
-
-
-
-
-
-
Variable clock
T
T
cy(CLK)
T
cy(CLK)
cy(CLK)
CCLK
CCLK
7.557
Max
520
12
50
15
8
8
8
0
-
-
-
-
-
-
-
-
-
− t
− t
⁄
⁄
+ 20
6
4
CHCX
CLCX
[1][2]
f
7.189
1333
1083
osc
Min
320
125
150
500
333
250
50
33
33
0
© NXP B.V. 2011. All rights reserved.
-
-
-
-
-
-
-
-
-
-
= 12 MHz Unit
7.557 MHz
Max
520
103
2.0
3.0
50
15
8
8
0
-
-
-
-
-
-
-
-
-
-
-
-
-
60 of 77
kHz
MHz
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns