STM32L151VB STMicroelectronics, STM32L151VB Datasheet - Page 73

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STM32L151VB

Manufacturer Part Number
STM32L151VB
Description
Ultra-low-power ARM Cortex-M3 MCU with 128 Kbytes Flash, 32 MHz CPU, LCD, USB
Manufacturer
STMicroelectronics
Datasheet

Specifications of STM32L151VB

Operating Power Supply Range
1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V (with BOR option)
Temperature Range
–40 to 85 °C
4 Modes
Sleep, Low-power run (9 μA at 32 kHz), Low-power sleep (4.4 μA),Stop with RTC (1.45 μA), Stop (570 nA), Standby (300 nA)
Ultralow Leakage Per I/o
50 nA
Fast Wakeup From Stop
8 μs
Core
ARM 32-bit Cortex™-M3 CPU
Dma
7-channel DMA controller, supporting timers, ADC, SPIs, I2Cs and USARTs

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STM32L151xx, STM32L152xx
6.3.12
Table 38.
1. Guaranteed by design.
2. FT = 5V tolerant. To sustain a voltage higher than V
3. Tested in production
4. 0.7V
5. FT = Five-volt tolerant.
6. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
7. With a minimum of 200 mV. Based on characterization, not tested in production.
8. The max. value may be exceeded if negative current is injected on adjacent pins.
Symbol
V
R
R
C
V
V
V
V
I
lkg
hys
PU
PD
IH
IH
IO
IL
IL
DD
Input low level voltage
Standard I/O input high level voltage
FT
Input low level voltage
Standard I/O Input high level voltage
FT
Standard I/O Schmitt trigger voltage
hysteresis
Input leakage current
Weak pull-up equivalent resistor
Weak pull-down equivalent resistor
I/O pin capacitance
for 5V-tolerant receiver
(2)
(5)
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in
performed under conditions summarized in
I/O static characteristics
I/O input high level voltage
I/O input high level voltage
(6)
Parameter
(8)(3)
(9)(3)
(9)(3)
Doc ID 17659 Rev 6
DD
I/Os with analog switches
I/Os with analog switches
+0.5 the internal pull-up/pull-down resistors must be disabled.
1.65 V
1.65 V
1.65 V
2.7 V
2.0 V
V
V
V
V
V
I/Os with USB
I/Os with LCD
Standard I/Os
CMOS ports
CMOS ports
CMOS ports
CMOS ports
Conditions
SS
SS
SS
SS
SS
TTL ports
V
V
and LCD
IN
IN
V
V
V
V
V
V
V
Table
V
V
V
=
=
DD
DD
IN
IN
IN
IN
IN
DD
DD
DD
V
V
DD
SS
V
V
V
V
V
3.6 V
3.6 V
3.6 V
3.6 V
2.0 V
DD
DD
DD
DD
DD
9. All I/Os are CMOS and TTL compliant.
Table 38
10% V
V
V
SS
DD
are derived from tests
–0.3
Min
2
0.7
30
30
(1)
(3)(4)
- 0.3
DD
Electrical characteristics
(7)
Typ
45
45
5
0.3V
V
V
DD
DD
5.5V
Max
5.25
TBD
±50
±50
±50
±50
0.8
5.5
60
60
+0.3
DD
+0.3
(3)
73/109
Unit
nA
pF
V

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