STM32L151VB STMicroelectronics, STM32L151VB Datasheet - Page 78

• Manufacturer Part Number: STM32L151VB
• Description: Ultra-low-power ARM Cortex-M3 MCU with 128 Kbytes Flash, 32 MHz CPU, LCD, USB
• Manufacturer: STMicroelectronics

Specifications of STM32L151VB

• Operating Power Supply Range: 1.65 V to 3.6 V (without BOR) or 1.8 V to 3.6 V (with BOR option)
• Temperature Range: –40 to 85 °C
• 4 Modes: Sleep, Low-power run (9 μA at 32 kHz), Low-power sleep (4.4 μA),Stop with RTC (1.45 μA), Stop (570 nA), Standby (300 nA)
• Ultralow Leakage Per I/o: 50 nA
• Fast Wakeup From Stop: 8 μs
• Core: ARM 32-bit Cortex™-M3 CPU
• Dma: 7-channel DMA controller, supporting timers, ADC, SPIs, I2Cs and USARTs

Electrical characteristics
6.3.15
78/109
Communications interfaces
I
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
summarized in
The line I
with the following restrictions: SDA and SCL are not “true” open-drain I/O pins. When
configured as open-drain, the PMOS connected between the I/O pin and V
but is still present.
The I
injection characteristics
(SDA and SCL) .
Table 43.
1. Guaranteed by design, not tested in production.
2. f
3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
2
t
C interface characteristics
w(STO:STA)
Symbol
t
t
t
t
t
w(SCLH)
w(SCLL)
t
su(SDA)
t
t
su(STO)
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
period of SCL signal.
undefined region of the falling edge of SCL.
t
t
t
su(STA)
h(SDA)
PCLK1
r(SDA)
h(STA)
r(SCL)
f(SDA)
f(SCL)
C
2
C characteristics are described in
b
must be at least 2 MHz to achieve standard mode I
2
C interface meets the requirements of the standard I
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Repeated Start condition
setup time
Stop condition setup time
Stop to Start condition time
(bus free)
Capacitive load for each bus
line
I
2
C characteristics
Table
Parameter
9.
for more details on the input/output alternate function characteristics
Doc ID 17659 Rev 6
Standard mode I
PCLK1
Table
Min
250
0
4.7
4.0
4.0
4.7
4.0
4.7
(3)
frequency and V
43. Refer also to
²
C frequencies. It must be at least 4 MHz to
Table 43
1000
Max
300
400
2
C
(1)
STM32L151xx, STM32L152xx
are derived from tests
20 + 0.1C
DD
2
Fast mode I
Section 6.3.11: I/O current
C communication protocol
Min
100
0
1.3
0.6
0.6
0.6
0.6
1.3
supply voltage conditions
(4)
b
DD
2
C
900
Max
300
300
400
(1)(2)
is disabled,
(3)
Unit
pF
µs
ns
µs
μs
μs