ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 161

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.7 SCI Synchronous Transmission
The SCI transmitter allows the user to control a
one way synchronous serial transmission. The
SCLK pin is the output of the SCI transmitter clock.
No clock pulses are sent to the SCLK pin during
start bit and stop bit. Depending on the state of the
LBCL bit in the SCICR3 register, clock pulses are
or are not be generated during the last valid data
bit (address mark). The CPOL bit in the SCICR3
register allows the user to select the clock polarity,
and the CPHA bit in the SCICR3 register allows
the user to select the phase of the external clock
(see
During idle, preamble and send break, the external
SCLK clock is not activated.
Figure 91. SCI Example of Synchronous and Asynchronous Transmission
Figure
91,
Figure 92
and
SCI
Figure
Output port
SCLK
TDO
RDI
93).
Data out
Data in
Data in
Clock
Enable
These options allow the user to serially control pe-
ripherals which consist of shift registers, without
losing any functions of the SCI transmitter which
can still talk to other SCI receivers. These options
do not affect the SCI receiver which is independ-
ent from the transmitter.
Note: The SCLK pin works in conjunction with the
TDO pin. When the SCI transmitter is disabled (TE
and RE = 0), the SCLK and TDO pins go into high
impedance state.
Note: The LBCL, CPOL and CPHA bits have to be
selected before enabling the transmitter to ensure
that the clock pulses function correctly. These bits
should not be changed while the transmitter is en-
abled.
Asynchronous
(e.g. modem)
Synchronous
(e.g. shift register)
ST72561
161/265