ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 64

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
PWM AUTO-RELOAD TIMER (Cont’d)
Independent PWM signal generation
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins with minimum core processing overhead.
This function is stopped during HALT mode.
Each PWMx output signal can be selected inde-
pendently using the corresponding OEx bit in the
PWM Control register (PWMCR). When this bit is
set, the corresponding I/O pin is configured as out-
put push-pull alternate function.
The PWM signals all have the same frequency
which is controlled by the counter period and the
ARTARR register value.
f
When a counter overflow occurs, the PWMx pin
level is changed depending on the corresponding
OPx (output polarity) bit in the PWMCR register.
Figure 42. PWM Auto-reload Timer Function
Figure 43. PWM Signal from 0% to 100% Duty Cycle
64/265
PWM
= f
AUTO-RELOAD
DUTY CYCLE
COUNTER
(PWMDCRx)
WITH OEx=1
AND OPx=0
REGISTER
REGISTER
WITH OEx=1
AND OPx=1
(ARTARR)
OCRx=FCh
OCRx=FDh
OCRx=FEh
OCRx=FFh
COUNTER
f
COUNTER
255
000
/ (256 - ARTARR)
FDh
FEh
ARTARR=FDh
FFh
FDh
When the counter reaches the value contained in
one of the output compare register (OCRx) the
corresponding PWMx pin level is restored.
It should be noted that the reload values will also
affect the value and the resolution of the duty cycle
of the PWM output signal. To obtain a signal on a
PWMx pin, the contents of the OCRx register must
be greater than the contents of the ARTARR reg-
ister.
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (256 - ARTARR)
Note: To get the maximum resolution (1/256), the
ARTARR register must be 0. With this maximum
resolution, 0% and 100% can be obtained by
changing the polarity.
FEh
FFh
FDh
FEh
t
t