ST72561AR7 STMicroelectronics, ST72561AR7 Datasheet - Page 211

• Manufacturer Part Number: ST72561AR7
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72561AR7

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

10-BIT A/D CONVERTER (ADC) (Cont’d)
10.10.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read / Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register or writing to
any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED A/D clock selection
This bit is set and cleared by software.
Table 35. A/D Clock Selection
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = SLOW A/D Clock Selection
This bit is set and cleared by software. It works to-
gether with the SPEED bit. Refer to
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
EOC SPEED ADON SLOW
7
f
f
CPU
CPU
SLOW=0, SPEED=0)
(where f
/2 (same frequency as
f
f
f
CPU
CPU
ADC
CPU
/2
/4
<= 4 MHz)
CH3
SLOW
CH2
0
0
1
1
Table
CH1
SPEED
35.
0
1
0
1
CH0
0
DATA REGISTER (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
DATA REGISTER (ADCDRL)
Read Only
Reset Value: 0000 0000 (00h)
Bits 7:2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Analog Converted Value
D9
7
7
0
Channel Pin*
D8
0
AIN10
AIN11
AIN12
AIN13
AIN14
AIN15
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
D7
0
D6
0
CH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D5
0
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D4
0
CH1
ST72561
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D3
D1
211/265
CH0
D2
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0