ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 73

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ST72324BK2

Manufacturer Part Number
ST72324BK2
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72324BK2

Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
ST72324Bxx
MCC beep control register (MCCBCR)
Table 41.
Table 42.
Table 43.
MCCBCR
7:2
1:0 BC[1:0]
Bit
Address
002Ch
002Dh
002Bh
(Hex.)
7
BC1
Name
0
0
1
1
-
Register label
SICSR
Reset value
MCCSR
Reset value
MCCBCR
Reset value
MCCBCR register description
Beep frequency selection
Main clock controller register map and reset values
Reserved, must be kept cleared
Beep Control
These 2 bits select the PF1 pin beep capability (see
signal is available in Active-halt mode but has to be disabled to reduce the
consumption.
6
BC0
0
1
0
1
MCO
5
7
0
0
0
Reserved
-
AVDIE
CP1
6
0
0
0
4
~500 Hz
~1 kHz
~2 kHz
AVDF
CP0
5
0
0
0
Beep mode with f
Function
LVDRF
3
SMS
4
0
0
x
Off
TB1
3
0
0
0
2
Table
OSC2
Reset value: 0000 0000 (00h)
= 8 MHz
TB0
42). The beep output
~50% duty cycle
2
0
0
0
On-chip peripherals
Beep signal
Output
1
BC1
OIE
BC[1:0]
1
0
0
0
R/W
WDGRF
BC0
0
OIF
73/193
0
0
0
x

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