ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 82

• Manufacturer Part Number: ST72324BK2
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BK2

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
Note:
82/193
1
2
3
4
5
If the timer clock is an external clock, the formula is:
Where:
Δt
f
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1.
2.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OC
●
●
●
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see
Figure 45 on page 83
PWM mode.
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OC
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced output compare capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
EXT
Reading the SR register while the OCFi bit is set.
An access (read or write) to the OCiLR register.
Write to the OCiHR register (further compares are inhibited).
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
for an example with f
i
R register and the OLVi bit should be changed after each
Δ OCiR = Δt
Figure 44 on page 83
i
R register:
CPU
/4). This behavior is the same in OPM or
*
f
EXT
for an example with f
ST72324Bxx
CPU
/2 and