ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 96
ST72324BK2
Manufacturer Part Number
ST72324BK2
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324BJ6.pdf
(193 pages)
Specifications of ST72324BK2
Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
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On-chip peripherals
Table 52.
10.4
10.4.1
10.4.2
Note:
96/193
Timer A: 36
Timer B: 46
Timer A: 37
Timer B: 47
Timer A: 3E
Timer B: 4E
Timer A: 3F
Timer B: 4F
Timer A: 38
Timer B: 48
Timer A: 39
Timer B: 49
Timer A: 3A
Timer B: 4A
Timer A: 3B
Timer B: 4B
Timer A: 3C
Timer B: 4C
Timer A: 3D
Timer B: 4D
Address
(Hex.)
16-bit timer register map and reset values (continued)
Serial peripheral interface (SPI)
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves.
However, the SPI interface can not be a master in a multi-master system.
Main features
●
●
●
●
●
●
●
●
●
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
OC1HR
Reset value
OC1LR
Reset value
OC2HR
Reset value
OC2LR
Reset value
CHR
Reset value
CLR
Reset value
ACHR
Reset value
ACLR
Reset value
IC2HR
Reset value
IC2LR
Reset value
Register
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
6 master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master mode fault and Overrun flags
CPU
label
/2 max. slave mode frequency (see note)
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
MSB
7
1
0
1
0
1
1
1
1
x
x
6
0
0
0
0
1
1
1
1
x
x
CPU
/4 max.)
5
0
0
0
0
1
1
1
1
x
x
4
0
0
0
0
1
1
1
1
x
x
3
0
0
0
0
1
1
1
1
x
x
2
0
0
0
0
1
1
1
1
x
x
1
0
0
0
0
1
0
1
0
x
x
ST72324Bxx
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
0
0
0
0
0
1
0
1
0
x
x
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