ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 98

• Manufacturer Part Number: ST72324BK2
• Description: 5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
• Manufacturer: STMicroelectronics

Specifications of ST72324BK2

• Hdflash Endurance: 1 kcycle at 55 °C, data retention 40 years at 85 °C
• Clock Sources: crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
• 4 Power Saving Modes: Slow, Wait, Active-halt, and Halt

On-chip peripherals
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The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in synchronized with the same clock signal (which is provided by the master device
via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see
slave must be programmed with the same timing mode.
Figure 51. Single master/single slave application
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
In Master mode:
Depending on the data/clock timing relationship, there are two cases in Slave mode (see
Figure
If CPHA = 1 (data latched on second clock edge):
If CPHA = 0 (data latched on first clock edge):
–
–
–
52):
SS internal must be held high continuously
SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to V
standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in
the in the SPICSR register)
SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see
collision error (WCOL) on page
MSB
generator
clock
8-bit Shift Register
SPI
Master
Figure
LSB
53).
MOSI
SCK
SS
MISO
102).
+5V
MISO
MOSI
SCK
SS
MSB
Not used if SS is managed
by software
Figure
8-bit Shift Register
SS
, or made free for
Slave
54) but master and
LSB
ST72324Bxx
Write