ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet
ST72561J6-Auto
Specifications of ST72561J6-Auto
Related parts for ST72561J6-Auto
ST72561J6-Auto Summary of contents
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... Full hardware/ software development package Table 1. Reference ST72561xx- Auto Doc ID 12370 Rev 8 ST72561xx-Auto LQFP44 10x10mm LQFP64 14x14mm Device summary Part number ST72561K4-Auto, ST72561K6-Auto, ST72561K7-Auto, ST72561K9-Auto, ST72561J4-Auto, ST72561J6-Auto, ST72561J7-Auto, ST72561J9-Auto, ST72561R4-Auto, ST72561R6-Auto, ST72561R7-Auto, ST72561R9-Auto, ST72561AR4-Auto, ST72561AR6-Auto, ST72561AR7-Auto, ST72561AR9-Auto www.st.com 1/324 1 ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72561-Auto 5.5.2 5.5.3 5.5.4 5.5.5 5.6 System integrity management (SI ...
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Contents 8.2.2 8.2.3 8.3 I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72561-Auto 11.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 12.7.8 12.7.9 12.7.10 Counter high register (CHR ...
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ST72561-Auto 14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 15.8 SCI mode register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8.1 ...
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ST72561-Auto 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 16.4.7 16.5 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 17.8.2 17.8.3 17.8.4 18 10-bit A/D converter (ADC ...
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ST72561-Auto 20.1.4 20.1.5 20.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 21 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72561-Auto List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72561-Auto Table 101. Peripheral consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72561-Auto Figure 49. Counter timing diagram, internal clock divided ...
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List of figures Figure 101. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72561-Auto Figure 153. ST72P561xxx-Auto FastROM commercial product structure . . . . . . . . . . . . . . . . . . . . . . 311 Figure 154. ST72561xx-Auto ROM commercial product structure . . ...
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Description 1 Description The ST72561xx-Auto devices are members of the ST7 microcontroller family designed for automotive mid-range applications with CAN (Controller Area Network) and LIN (Local Interconnect Network) interface. All devices are based on a common industry-standard 8-bit core, featuring ...
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ST72561-Auto Figure 1. Device block diagram OSC1 OSC2 RESET 1 TLI 1. On some devices only (see option PLL x 2 OSC /2 POWER SUPPLY CONTROL 8-BIT CORE ALU PROGRAM MEMORY ( Kbytes) RAM ...
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Description 1.1 Pin description Figure 2. LQFP 64-pin package pinout ARTIC1 / PA0 PWM0 / PA1 PWM1 / (HS) PA2 PWM2 / PA3 PWM3 / PA4 ARTCLK / (HS)PA5 ARTIC2 / (HS) PA6 T8_OCMP2 / PA7 T8_ICAP2 / PB0 T8_OCMP1 ...
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ST72561-Auto Figure 3. LQFP 44-pin package pinout ARTCLK / (HS)PA5 ARTIC2 / (HS) PA6 T8_OCMP1 / PB1 OSC1 1 ei3 OSC2 2 PWM0 / PA1 3 PWM1 / (HS) ...
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Description Figure 4. LQFP 32-pin package pinout For external pin connection guidelines, refer to 24/324 OSC1 1 ei3 OSC2 2 ei3 PWM0 / PA1 3 PWM1 / (HS) PA2 4 ei0 ARTCLK ...
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ST72561-Auto List of abbreviations used in Type: In/Output level: C Output level: Input: Output: Refer to Chapter 8: I/O ports The RESET configuration of each pin is shown in bold which is valid as long as the device is in ...
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Description Table 3. Device pin description (continued) Pin n° Pin name PE2 / AIN14 PE3 / AIN15 PB5 / AIN1 / ICCDATA I/O C PB6 / AIN2 / ...
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ST72561-Auto Table 3. Device pin description (continued) Pin n° Pin name PE7 PF0 PF1 / AIN7 PF2 / AIN8 PD1 / SCI1_RDI ...
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Register and memory map 2 Register and memory map As shown in Figure registers. The available memory locations consist of 128 bytes of register locations Kbytes of RAM and Kbytes of user program memory. ...
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ST72561-Auto Table 4. Hardware register map (continued) Register Address Block label 000Fh PFDR 0010h Port F PFDDR 0011h PFOR 0012h to Reserved Area (15 bytes) 0020h 0021h SPIDR 0022h SPI SPICR 0023h SPICSR 0024h FLASH FCSR 0025h ISPR0 0026h ISPR1 ...
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Register and memory map Table 4. Hardware register map (continued) Register Address Block label 0048h SCI1ISR 0049h SCI1DR 004Ah SCI1BRR LINSCI1 004Bh SCI1CR1 (LIN 004Ch SCI1CR2 Master/Slave) 004Dh SCI1CR3 004Eh SCI1ERPR 004Fh SCI1ETPR 0050h 0051h T16CR2 0052h T16CR1 0053h T16CSR ...
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ST72561-Auto Table 4. Hardware register map (continued) Register Address Block label 0068h CMCR 0069h CMSR 006Ah CTSR 006Bh CTPR 006Ch CRFR 006Dh CIER 006Eh CDGR 006Fh CPSR 0070h 0071h 0072h 0073h Active CAN 0074h 0075h 0076h 0077h PAGES 0078h 0079h ...
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Flash program memory 3 Flash program memory 3.1 Introduction The ST7 dual voltage High Density Flash (HDFlash non-volatile memory that can be electrically erased as a single block or by individual sectors and programmed on a Byte-by- Byte ...
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ST72561-Auto 3.3.1 Read-out protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level ...
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... Depending on the ICP code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection serial communication interface for downloading). When using an STMicroelectronics or third-party programming tool that supports ICP and the specific microcontroller device, the user needs only to implement the ICP hardware 34/324 ...
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ST72561-Auto interface on the application board (see to the device pinout description. 3.6 IAP (in-application programming) This mode uses a Bootloader program previously stored in Sector 0 by the user (in ICP mode or by plugging the device in a ...
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Central processing unit 4 Central processing unit 4.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 4.2 Main features ● Enable executing 63 basic instructions ● Fast 8-bit by 8-bit ...
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ST72561-Auto Figure 8. CPU registers PCH 15 RESET VALUE = RESET VECTOR @ FFFEh-FFFFh RESET VALUE = 1 15 RESET VALUE = STACK HIGHER ADDRESS 4.3.4 Condition code register (CC) Read/ write Reset value: 111x1xxx The 8-bit ...
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Central processing unit This bit is accessed by the JRMI and JRPL instructions. Bit Zero. This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation ...
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ST72561-Auto 4.3.5 Stack pointer (SP) Read/ write Reset value: 01 FFh SP7 SP6 The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack then decremented ...
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Central processing unit Figure 9. Stack manipulation example CALL Subroutine @ 0100h SP PCH @ 01FFh PCL Stack Higher Address = 01FFh Stack Lower Address = 0100h 40/324 PUSH Y Interrupt Event ...
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ST72561-Auto 5 Supply, reset and clock management 5.1 Introduction The device includes a range of utility features for securing the application in critical situations (for example, in case of a power brown-out), and reducing the number of external components. An ...
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Supply, reset and clock management Figure 11. Clock, reset and supply block diagram OSC2 OSC1 RESET 5.4 Multi-oscillator (MO) The main clock of the ST7 can be generated by two different source types coming from the ...
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ST72561-Auto output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Table 8. ST7 ...
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Supply, reset and clock management The reset vector fetch phase duration is two clock cycles. Figure 12. RESET sequence phases 5.5.2 Asynchronous external RESET pin The RESET pin is both an input and an open-drain output with integrated R resistor. ...
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ST72561-Auto The device RESET pin acts as an output that is pulled low when V V < V (falling edge) as shown in DD IT- The LVD filters spikes on V 5.5.5 Internal watchdog reset The RESET sequence generated by ...
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Supply, reset and clock management The LVD function is illustrated in Provided the minimum V the MCU can only be in two modes: ● under full software control ● in static safe reset In these conditions, secure operation is always ...
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ST72561-Auto greater than 256 or 4096 cycles then: rv ● If the AVD interrupt is enabled before the V interrupts will be received: The first when the AVDIE bit is set and the second when the threshold ...
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Supply, reset and clock management 5.6.5 Register description System integrity (SI) control/status register (SICSR) Read/Write Reset value: 000x 000x (00h AVDIE Bit 7 = Reserved, must be kept cleared. Bit 6 = AVDIE Voltage Detector interrupt enable This ...
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ST72561-Auto Table 11. Reset source flags External RESET pin Watchdog LVD Application notes The LVDRF flag is not cleared when another RESET type occurs (external or watchdog), the LVDRF flag remains set to keep trace of the original failure. In ...
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Interrupts 6 Interrupts 6.1 Introduction The ST7 enhanced interrupt management provides the following features: ● Hardware interrupts ● Software interrupt (TRAP) ● Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable ...
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ST72561-Auto Table 12. Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 17. Interrupt processing flowchart RESET RESTORE PC FROM STACK Servicing pending interrupts As several ...
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Interrupts When an interrupt request is not serviced immediately latched and then processed when its software priority combined with the hardware priority becomes the highest one. Note: 1 The hardware priority is exclusive while the software one is ...
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ST72561-Auto if the corresponding enable bit is set in the peripheral control register. The general sequence for clearing an interrupt is based on an access to the status register followed by a read or write to an associated register. Note: ...
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Interrupts Figure 20. Nested interrupt management RIM MAIN 6.5 Interrupt register description 6.5.1 CPU CC register interrupt bits Read/Write Reset value: 111x 1010 (xAh Bit I1, I0 Software Interrupt Priority These ...
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ST72561-Auto 6.5.2 Interrupt software priority registers (ISPRX) Read/ write (bit 7:4 of ISPR3 are read only) Reset value: 1111 1111 (FFh) ISPR0 ISPR1 ISPR2 ISPR3 These four registers contain the interrupt software priority of each interrupt vector. ● Each interrupt ...
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Interrupts Table 15. Dedicated interrupt instruction set (continued) Instruction POP CC Pop CC from the Stack RIM Enable interrupt (level 0 set) SIM Disable interrupt (level 3 set) TRAP Software trap WFI Wait for interrupt Note: During the execution of ...
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ST72561-Auto Table 16. Interrupt mapping Source N° block RESET Reset TRAP Software interrupt 0 TLI External top level interrupt 1 MCC/RTC Main clock controller time base interrupt 2 ei0/AWUFH External interrupt ei0/ Auto wake-up from Halt External interrupt ei1/Auxiliary Voltage ...
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Interrupts 6.6 External interrupts 6.6.1 I/O port interrupt sensitivity The external interrupt sensitivity is controlled by the ISxx bits in the EICR register (Figure 21). This control allows up to four fully independent external interrupt source sensitivities. Each external interrupt ...
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ST72561-Auto Figure 21. External interrupt control bits PORT A [7:0] INTERRUPTS PAOR.0 PADDR.0 PA0 PORT B [5:0] INTERRUPTS PBOR.0 PBDDR.0 PB0 PORT C [2:1] INTERRUPTS PCOR.7 PCDDR.7 PC1 PORT D [7:6, 4, 1:0] INTERRUPTS PDOR.0 PDDDR.0 PD0 EICR IS00 IS01 ...
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Interrupts 6.6.2 Register description External interrupt control register 0 (EICR0) Read/Write Reset value: 0000 0000 (00h) 7 IS31 IS30 Bits 7:6 = IS3[1:0] ei3 sensitivity The interrupt sensitivity, defined using the IS3[1:0] bits, is applied to the ei3 external interrupts: ...
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ST72561-Auto Table 19. Interrupt sensitivity - ei1 IS11 IS10 These 2 bits can be written only when I1 and I0 of the CC register are both set to 1 (level 3). Bits 1:0 = IS0[1:0] ei0 sensitivity ...
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Interrupts Table 21. Nested interrupts register map and reset values Address Register 7 (Hex.) label 0025h ISPR0 I1_3 Reset value 1 CAN TX/ER/SC 0026h ISPR1 I1_7 Reset value 1 0027h ISPR2 I1_11 Reset value 1 0028h ISPR3 Reset value 1 ...
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ST72561-Auto 7 Power saving modes 7.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, five main power saving modes are implemented in the ST7 (see ● Slow ● Wait (and Slow-Wait) ● ...
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Power saving modes In this mode, the master clock frequency (f and peripherals are clocked at this lower frequency (f Note: SLOW-WAIT mode is activated by entering WAIT mode while the device is in SLOW mode. Figure 23. SLOW mode ...
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ST72561-Auto Figure 24. WAIT mode flow-chart Note: Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are set to the current software priority level of the interrupt routine and recovered ...
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Power saving modes system is enabled, can generate a Watchdog RESET (see more details). Figure 25. HALT timing overview Figure 26. HALT mode flow-chart Note: 1 WDGHALT is an option bit. See option byte section for more details. 2 Peripheral ...
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ST72561-Auto Halt mode recommendations ● Make sure that an external event is available to wake up the microcontroller from Halt mode. ● When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with ...
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Power saving modes Note: As soon as active halt is enabled, executing a HALT instruction while the Watchdog is active does not generate a RESET. This means that the device cannot spend more than a defined delay in this power ...
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ST72561-Auto It is entered by executing the HALT instruction when the AWUEN bit in the AWUCSR register has been set and the OIE bit in the MCCSR register is cleared (see Main clock controller with real time clock MCC/RTC Figure ...
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Power saving modes Figure 30. AWUF halt timing diagram RUN MODE f CPU f AWU_RC AWUFH interrupt Figure 31. AWUFH mode flow-chart Note: 1 WDGHALT is an option bit. See option byte section for more details. 2 Peripheral clocked with ...
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ST72561-Auto 7.6.1 Register description AWUFH control/status register (AWUCSR) Read/Write (except bit 2 read only) Reset value: 0000 0000 (00h Bits 7:3 = Reserved. Bit 2 = AWUF Auto Wake-Up Flag This bit is set by hardware when ...
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Power saving modes Table 23. AWUPR prescaler (continued) AWUPR[7:0 FEh FFh In AWU mode, the period that the MCU stays in Halt Mode (t × AWUP AWU This prescaler register can be programmed to modify the time ...
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ST72561-Auto 8 I/O ports 8.1 Introduction The I/O ports offer different functional modes: ● transfer of data through digital inputs and outputs and for specific pins: ● external interrupt generation ● alternate signal input/output for the on-chip peripherals. An I/O ...
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I/O ports Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout description and interrupt section). If several input pins are selected simultaneously as interrupt sources, these are first detected according to the sensitivity ...
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ST72561-Auto Figure 32. I/O port general block diagram REGISTER ACCESS DR DDR OR OR SEL DDR SEL DR SEL EXTERNAL INTERRUPT SOURCE ( Table 26. I/O port mode options Configuration mode Floating with/without Interrupt Input Pull-up with/without Interrupt ...
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I/O ports Table 27. I/O port configurations NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS NOT IMPLEMENTED IN TRUE OPEN DRAIN I/O PORTS 1. When the I/O port is in input configuration ...
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ST72561-Auto Warning: 8.3 I/O port implementation The hardware implementation on each I/O port depends on the settings in the DDR and OR registers and specific feature of the I/O port such as ADC Input or true open drain. Switching these ...
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I/O ports 8.4.2 Interrupt ports Table 29. Configuration of PA0 PB0, 2,4; PC1; PD0,6 (with pull-up) Floating input Pull-up interrupt input Open drain output Push-pull output Table 30. Configuration of PA1 PB1,3,5; PC2; PD1, ...
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ST72561-Auto 8.4.3 Pull-up input port (CANTX requirement) Table 31. Configuration of PC4 The PC4 port cannot operate as a general purpose output. The CAN peripheral controls it directly when enabled. Otherwise, PC4 is a pull-up input. If DDR = 1 ...
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I/O ports Table 32. Port configuration (continued) Port Pin name PD0 PD1 PD3:2 Port D PD4 PD5 PD6 PD7 Port E PE7:0 Port F PF7:0 1. When the CANTX alternate function is selected, the I/O port operates in output push-pull ...
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ST72561-Auto Table 35. I/O port register map and reset values Address Register (Hex.) label Reset value of all IO port registers 0000h PADR 0001h PADDR 0002h PAOR 0003h PBDR 0004h PBDDR 0005h PBOR 0006h PCDR 0007h PCDDR 0008h PCOR 0009h ...
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Window watchdog (WWDG) 9 Window watchdog (WWDG) 9.1 Introduction The Window Watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its ...
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ST72561-Auto Figure 34. Watchdog block diagram RESET The application program must write in the WDGCR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the ...
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Window watchdog (WWDG) 9.4 Using halt mode with the WDG If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT instruction recommended before executing the HALT instruction to refresh the WDG counter, to ...
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ST72561-Auto Figure 36. Exact timeout duration (t WHERE (LSB + 128 min0 t = 16384 x t max0 t = 125ns if f OSC2 CNT = Value of T[5:0] bits in the WDGCR register ...
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Window watchdog (WWDG) Figure 37. Window watchdog timing diagram 9.6 Low power modes Table 36. Effect of low power modes on WDG Mode SLOW No effect on Watchdog: the downcounter continues to decrement at normal speed. WAIT No effect on ...
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ST72561-Auto 9.8 Using halt mode with the WDG (WDGHALT option) The following recommendation applies if Halt mode is used when the watchdog is enabled. ● Before executing the HALT instruction, refresh the WDG counter, to avoid an unexpected WDG reset ...
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Window watchdog (WWDG) Table 37. Watchdog timer register map and reset values Address (Hex 88/324 Register label 7 WDGCR WDGA Reset value 0 WDGWR - Reset value 0 Doc ID 12370 Rev 8 ST72561-Auto ...
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ST72561-Auto 10 Main clock controller with real time clock MCC/RTC The Main Clock Controller consists of three different functions: ● a programmable CPU clock prescaler ● a clock-out signal to supply external devices ● a real time clock timer with ...
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Main clock controller with real time clock MCC/RTC 10.4 Low power modes Table 38. Effect of low power modes on MCC/RTC Mode No effect on MCC/RTC peripheral. WAIT MCC/RTC interrupt cause the device to exit from WAIT mode. No effect ...
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ST72561-Auto Table 40. CPU clock frequency in SLOW mode OSC2 OSC2 OSC2 OSC2 Bit 4 = SMS Slow mode select This bit is set and cleared by ...
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Main clock controller with real time clock MCC/RTC Caution: The BRES and BSET instructions must not be used on the MCCSR register to avoid unintentionally clearing the OIF bit. Table 42. Main clock controller register map and reset values Address ...
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ST72561-Auto 11 PWM auto-reload timer (ART) 11.1 Introduction The Pulse Width Modulated Auto-Reload Timer on-chip peripheral consists of an 8-bit auto- reload counter with compare/capture capabilities and of a 7-bit prescaler clock source. These resources allow five possible operating modes: ...
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PWM auto-reload timer (ART) 11.2 Functional description 11.2.1 Counter The free running 8-bit counter is fed by the output of the prescaler, and is incremented on every rising edge of the clock signal possible to read or write ...
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ST72561-Auto Figure 40. Output compare control f COUNTER COUNTER OCRx PWMDCRx PWMx 11.2.5 Independent PWM signal generation This mode allows up to four Pulse Width Modulated signals to be generated on the PWMx output pins with minimum core processing overhead. ...
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PWM auto-reload timer (ART) Figure 42. PWM signal from 0% to 100% duty cycle COUNTER OCRx=FCh OCRx=FDh OCRx=FEh OCRx=FFh 11.2.6 Output compare and Time base interrupt On overflow, the OVF flag of the ARTCSR register is set and an overflow ...
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ST72561-Auto Each input capture can generate an interrupt independently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status register (ARTICCSR). These input capture interrupts are enabled ...
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PWM auto-reload timer (ART) Figure 45. Input capture timing diagram CPU f COUNTER COUNTER ARTICx PIN CFx FLAG ICRx REGISTER f CPU f COUNTER COUNTER ARTICx PIN CFx FLAG ICRx REGISTER 11.2.9 External interrupt capability This mode allows ...
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ST72561-Auto 11.3 Register description Control/status register (ARTCSR) Read/Write Reset value: 0000 0000 (00h) 7 EXCL CC2 Bit 7 = EXCL External Clock This bit is set and cleared by software. It selects the input clock for the 7-bit prescaler. 0: ...
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PWM auto-reload timer (ART) Bit 0 = OVF Overflow Flag This bit is set by hardware and cleared by software reading the ARTCSR register. It indicates the transition of the counter from FFh to the ARTARR value 0: New transition ...
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ST72561-Auto PWM control register (PWMCR) Read/write Reset value: 0000 0000 (00h) 7 OE3 OE2 Bit 7:4 = OE[3:0] PWM Output Enable These bits are set and cleared by software. They enable or disable the PWM output channels independently acting on ...
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PWM auto-reload timer (ART Bit 7:6 = Reserved, always read as 0. Bit 5:4 = CS[2:1] Capture Sensitivity These bits are set and cleared by software. They determine the trigger event polarity on the corresponding input capture ...
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ST72561-Auto Table 46. PWM auto-reload timer register map and reset values (continued) Address Register label (Hex.) PWMCR 0035h Reset value ARTCSR 0036h Reset value ARTCAR 0037h Reset value ARTARR 0038h Reset value ARTICCSR 0039h Reset value ARTICR1 003Ah Reset value ...
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Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input ...
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ST72561-Auto 12.3 Functional description 12.3.1 Counter The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high and low. Counter Register ...
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Figure 47. Timer block diagram f CPU 1/2 1/4 1/8 EXTCLK pin CC[1:0] ICF1 OCF1 TOF ICIE OCIE TOIE TIMER INTERRUPT Figure 48. 16-bit read sequence: (from counter or alternate counter register) 106/324 ST7 INTERNAL BUS MCU-PERIPHERAL INTERFACE ...
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ST72561-Auto The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After ...
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Figure 49. Counter timing diagram, internal clock divided by 2 TIMER OVERFLOW FLAG (TOF) Figure 50. Counter timing diagram, internal clock divided by 4 COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 51. Counter timing diagram, internal clock divided ...
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ST72561-Auto The active transition is software programmable through the IEDGi bit in the control register (CRi). Timing resolution is one count of the free running counter: ( 12.3.4 Procedure To use the input capture function select the following in the ...
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Figure 52. Input capture block diagram ICAP1 pin EDGE DETECT ICAP2 pin IC2R Register 16-BIT Figure 53. Input capture timing diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER Note: The rising edge is the active ...
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ST72561-Auto These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC Timing resolution is one count of the free running counter: ( 12.3.6 Procedure To use the output compare function, ...
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The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OC ● Write to the OCiHR register (further compares are inhibited). ● Read the ...
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ST72561-Auto Figure 55. Output compare timing diagram, f OUTPUT COMPARE REGISTER i (OCRi) Figure 56. Output compare timing diagram, f OUTPUT COMPARE REGISTER i (OCRi) 12.3.8 One pulse mode One Pulse mode enables the generation of a pulse when an ...
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Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Then, ...
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ST72561-Auto Note: 1 The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2 When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both ...
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Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding ...
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ST72561-Auto f = External timer clock frequency (in hertz) EXT The Output Compare 2 event causes the counter to be initialized to FFFCh (See Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited ...
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Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is ...
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ST72561-Auto Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. This bit is ...
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Bit 5 = OPM One Pulse Mode. 0: One Pulse mode is not active. 1: One Pulse mode is active, the ICAP1 pin can be used to trigger one pulse on the OCMP1 pin; the active transition is ...
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ST72561-Auto Bit 6 = OCF1 Output Compare Flag 1. 0: nomatch (reset value). 1: the content of the free running counter has matched the content of the OC1R register. To clear this bit, first read the SR register, then read ...
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Input capture 1 low register (IC1LR) Read only Reset value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 MSB 12.7.6 ...
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ST72561-Auto 12.7.9 Output compare 2 low register (OC2LR) Read/ write Reset value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. 7 MSB 12.7.10 Counter high ...
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Alternate counter low register (ACLR) Read only Reset value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to ...
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ST72561-Auto Table 51. 16-bit timer register map (continued) Address Register name (Hex.) 54 IC1HR 55 IC1LR 56 OC1HR 57 OC1LR 58 CHR 59 CLR 5A ACHR 5B ACLR 5C IC2HR 5D IC2LR 5E OC2HR 5F OC2LR ...
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Introduction The timer consists of a 8-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input ...
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ST72561-Auto Writing in the CTR register or ACTR register resets the free running counter to the FCh value. Both counters have a reset value of FCh (this is the only value which is reloaded in the 8-bit timer). The reset ...
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Figure 59. Timer block diagram f CPU f 1/8000 OSC2 CC[1:0] ICF1 ICIE OCIE TOIE TIMER INTERRUPT Whatever the timer mode used (input capture, output compare, one pulse mode or PWM mode) an overflow occurs when the ...
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ST72561-Auto 1. Reading the SR register while the TOF bit is set access (read or write) to the CTR register. Note: The TOF bit is not cleared by accesses to ACTR register. The advantage of accessing the ACTR ...
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Input capture In this section, the index, i, may because there are two input capture functions in the 8-bit timer. The two 8-bit input capture registers (IC1R and IC2R) are used to ...
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ST72561-Auto Moreover if one of the ICAPi pins is configured as an input and the second one as an output, an interrupt can be generated if the user toggles the output pin and if the ICIE bit is set. 6 ...
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These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC Timing resolution is one count of the free running counter: (f Procedure To use the output compare ...
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ST72561-Auto When the timer clock is f counter value equals the OCiR register value plus 1 (see 4 The output compare functions can be used both for generating external events on the OCMPi pins even if the input capture mode ...
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Figure 67. Output compare timing diagram, f OUTPUT COMPARE REGISTER i (OCRi) 13.3.5 One pulse mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM ...
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ST72561-Auto Then valid event on the ICAP1 pin, the counter is initialized to FCh and OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. ...
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Figure 68. One pulse mode timing example COUNTER Note: IEDG1 = 1, OC1R = D0h, OLVL1 = 0, OLVL2 = 1 Figure 69. Pulse width modulation mode timing example Note: OC1R = D0h, OC2R = E2, OLVL1 ...
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ST72561-Auto 1. Load the OC2R register with the value corresponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corresponding to the period of the pulse if (OLVL1 ...
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IC2R can be loaded) but the user must take care that the counter is reset each period and ICF1 can also generates interrupt if ICIE is set. 4 When the Pulse Width Modulation (PWM) and ...
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ST72561-Auto 13.6 Summary of timer modes Table 54. Timer modes Modes Input Capture (1 and/or 2) Output Compare (1 and/or 2) One Pulse Mode PWM Mode 1. See note 4 in One pulse 2. See note 5 in One pulse ...
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Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software effect on the OCMP2 pin. 1:Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E ...
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ST72561-Auto Bit 4 = PWM Pulse Width Modulation. 0: PWM mode is not active. 1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the length of the pulse depends on the value of OC1R register; the ...
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Note: Reading or writing the ACTR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag input capture (reset value input capture has occurred on the ICAP2 pin. To clear ...
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ST72561-Auto 13.7.6 Output compare 2 register (OC2R) Read/ write Reset value: 0000 0000 (00h) This is an 8-bit register that contains the value to be compared to the CTR register. 7 MSB 13.7.7 Counter register (CTR) Read only Reset value: ...
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Address Register name (Hex.) 3C CR2 3D CR1 3E CSR 3F IC1R 40 OC1R 41 CTR 42 ACTR 43 IC2R 44 OC2R 144/324 OC1E OC2E OPM PWM ICIE ...
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ST72561-Auto 14 Serial peripheral interface (SPI) 14.1 Introduction The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices ...
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Serial peripheral interface (SPI) Figure 70. Serial peripheral interface block diagram MOSI MISO SOD bit SCK SS 14.3.1 Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure The MOSI pins ...
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ST72561-Auto Figure 71. Single master/ single slave application MASTER MSBit 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR 14.3.2 Slave select management As an alternative to using the SS pin to control the Slave Select signal, the application can choose to manage ...
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Serial peripheral interface (SPI) Figure 73. Hardware/software slave select management 14.3.3 Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description ...
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ST72561-Auto 14.3.5 Slave mode operation In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the following actions: – ...
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Serial peripheral interface (SPI) MISO pin and the MOSI pin are directly connected between the master and the slave device. Note: If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. ...
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ST72561-Auto Clearing the MODF bit is done through a software sequence read access to the SPICSR register while the MODF bit is set write to the SPICR register. Note: To avoid any conflicts in an application ...
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Serial peripheral interface (SPI) Figure 75. Clearing the WCOL bit (write collision flag) software sequence Clearing sequence after SPIF = 1 (end of a data byte transfer) 1st Step 2nd Step Clearing sequence before SPIF = 1 (during a data ...
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ST72561-Auto Figure 76. Single master / multiple slave configuration SCK MOSI SCK 5V SS 14.6 Low power modes Table 56. Effect of low power modes on SPI Mode WAIT HALT Using the SPI to wake up the device from halt ...
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Serial peripheral interface (SPI) 14.7 Interrupts Table 57. SPI interrupt control and wake-up capability Interrupt event SPI End of Transfer Event Master Mode Fault Event Overrun Error Note: The SPI interrupt events are connected to the same interrupt vector (see ...
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ST72561-Auto Bit 4 = MSTR Master Mode This bit is set and cleared by software also cleared by hardware when, in master mode (see Master mode fault 0: Slave mode 1: Master mode. The function ...
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Serial peripheral interface (SPI) SPIE = 1 in the SPICR register cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in ...
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ST72561-Auto 14.8.3 Data I/O register (SPIDR) Read/ write Reset value: Undefined The SPIDR register is used to transmit and receive data on the serial bus master device, a write to this register will initiate transmission/reception ...
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LINSCI serial communication interface (LIN master/slave) 15 LINSCI serial communication interface (LIN master/slave) 15.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. ...
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ST72561-Auto 15.3 LIN features ● LIN master – 13-bit LIN synch break generation ● LIN slave – Automatic header handling – Automatic baud rate resynchronization based on recognition and measurement of the LIN synch field (for LIN slave nodes) – ...
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LINSCI serial communication interface (LIN master/slave) Figure 77. SCI block diagram (in conventional baud rate generator mode) TDO RDI SCICR2 TIE 15.5 SCI mode - functional description 15.5.1 Conventional baud rate generator mode The block diagram of the serial control ...
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ST72561-Auto 15.5.2 Extended prescaler mode Two additional prescalers are available in extended prescaler mode. They are shown in Figure 79. ● An extended prescaler receiver register (SCIERPR) ● An extended prescaler transmitter register (SCIETPR) 15.5.3 Serial data format Word length ...
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LINSCI serial communication interface (LIN master/slave) Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the ...
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ST72561-Auto Idle line Setting the TE bit drives the SCI to send a preamble consecutive ‘1’s (idle line) before the first character. In this case, clearing and then setting the ...
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LINSCI serial communication interface (LIN master/slave) When an overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. ● The shift register will be overwritten. ● An interrupt is generated if the RIE ...
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ST72561-Auto with (see SCP[1:0] bits 16, 32, 64,128 (see SCT[2:0] bits 16, 32, 64,128 (see SCR[2:0] bits) All these bits are ...
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LINSCI serial communication interface (LIN master/slave) Figure 79. SCI baud rate and extended prescaler block diagram f CPU /16 15.5.7 Receiver muting and wake-up feature In multiprocessor configurations it is often desirable that only the intended message recipient should actively ...
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ST72561-Auto Idle line detection Receiver wakes up by idle line detection when the receive line has recognized an Idle Line. Then the RWU bit is reset by hardware but the IDLE bit is not set. This feature is useful in ...
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LINSCI serial communication interface (LIN master/slave) Example 2: data = 00110101; 4 bits set => parity bit will even parity is selected (PS bit = 0). Odd parity The parity bit is calculated to obtain an odd ...
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ST72561-Auto The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). ...
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LINSCI serial communication interface (LIN master/slave) The OR bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register whereas RDRF is still set. An interrupt is ...
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ST72561-Auto Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and ...
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LINSCI serial communication interface (LIN master/slave) Bit 6 = TCIE Transmission complete interrupt enable This bit is set and cleared by software. 0: interrupt is inhibited 1: an SCI interrupt is generated whenever the SCISR register ...
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ST72561-Auto Contains the received or transmitted data character, depending on whether it is read from or written to. 7 DR7 DR6 The data register performs a double function (read and write) since it is composed of two registers, one for ...
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LINSCI serial communication interface (LIN master/slave) Table 64. Transmitter rate divider TR dividing factor Bits 2:0 = SCR[2:0] SCI Receiver rate divider. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock ...
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ST72561-Auto 15.8.7 Extended transmit prescaler division register (SCIETPR) Read/ write Reset value: 0000 0000 (00h) 7 ETPR7 ETPR6 Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended baud rate generator is activated when a value other than 00h ...
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LINSCI serial communication interface (LIN master/slave) In LIN Slave mode the LIN baud rate generator is selected instead of the conventional or extended prescaler. The LIN baud rate generator is common to the transmitter and the receiver. Then the baud ...
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ST72561-Auto Figure 81. SCI block diagram in LIN slave mode TDO RDI 15.9.3 LIN reception In LIN mode the reception of a byte is the same as in SCI mode but the LINSCI has features for handling the LIN header ...
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LINSCI serial communication interface (LIN master/slave) Note recommended to combine the header detection function with Mute mode. Putting the LINSCI in mute mode allows the detection of Headers only and prevents the reception of any other characters. This ...
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ST72561-Auto 15.9.4 LIN error detection LIN header error flag The LIN header error flag indicates that an invalid LIN header has been detected. When a LIN header error occurs: ● The LHE flag is set ● An interrupt is generated ...
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LINSCI serial communication interface (LIN master/slave) If the LHE flag is set, it means that: D > 15.625% If LHE flag is not set, it means that: D < 16.40625% If 15.625% ≤ D < 16.40625%, then the flag can ...
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ST72561-Auto worst case: This occurs when the LIN identifier lasts exactly 10 T case, the LIN break and synch fields last 39T Assuming the slave measures these first 39 bits with a desynchronized clock of 15.5%. ...
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LINSCI serial communication interface (LIN master/slave) 15.9.5 LIN baud rate Baud rate programming is done by writing a value in the LPR prescaler or performing an automatic resynchronization as described below. Automatic resynchronization To automatically adjust the baud rate based ...
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ST72561-Auto Figure 84. LDIV read / write operations when LDUM = 0 Write LPR Figure 85. LDIV read / write operations when LDUM = 1 Write LPR 15.9.7 LINSCI clock tolerance LINSCI clock tolerance when unsynchronized When LIN slaves are ...
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LINSCI serial communication interface (LIN master/slave) Note: If the period desynchronization of the slave is +15% (slave too slow), the character “00h” which represents a sequence of 9 low bits must not be interpreted as a break character (9 bits ...
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ST72561-Auto 15.9.9 Error due to LIN synch measurement The LIN synch field is measured over eight bit times. This measurement is performed using a counter clocked by the CPU clock. The edge detections are performed using the CPU clock cycle. ...
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LINSCI serial communication interface (LIN master/slave) 15.10 LIN mode register description 15.10.1 Status register (SCISR) Read only Reset value: 1100 0000 (C0h) 7 TDRE TC Bits 7:4 = same function as in SCI mode, please refer to description. Bit 3 ...
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ST72561-Auto 15.10.2 Control Register 1 (SCICR1) Read/ write Reset value: x000 0000 (x0h Bits 7:3 = Same function as in SCI mode, please refer to description. Bit 2 = PCE Parity control enable. This bit is set ...
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LINSCI serial communication interface (LIN master/slave) 15.10.4 Control register 3 (SCICR3) Read/ write Reset value: 0000 0000 (00h) 7 LDUM LINE Bit 7 = LDUM LIN Divider Update Method. This bit is set and cleared by software and is also ...
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ST72561-Auto Bit 4 = LASE LIN Auto Synch Enable. This bit enables the Auto Synch Unit (ASU set and cleared by software only usable in LIN Slave mode. 0: auto synch unit disabled 1: auto synch ...
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LINSCI serial communication interface (LIN master/slave) 15.10.5 LIN divider registers LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is accessible at the address of the SCIBRR register and the LPFR register ...
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ST72561-Auto Table 68. LDIV fraction LPFR[3: ... When initializing LDIV, the LPFR register must be written first. Then, the write to the LPR register will effectively update LDIV and so the clock generation ...
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LINSCI serial communication interface (LIN master/slave) 15.10.8 LIN header length register (LHLR) Read only Reset value: 0000 0000 (00h LHL7 LHL6 Note: In LIN slave mode when LASE = 1 or LHDM = 1, the LHLR register is ...
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ST72561-Auto Table 70. LHL fraction coding LHL[1: Example of LHL coding Example 1: LHL = 33h = 001100 11b LHL(7:3) = 1100b = 12d LHL(1:0) = 11b = 3d This leads to: Mantissa ( ...
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LINSCI serial communication interface (LIN master/slave) Table 71. LINSCI1 register map and reset values Addr. Register name (Hex.) SCI1SR 48 Reset value SCI1DR 49 Reset value SCI1BRR 4A LPR (LIN Slave Mode) Reset value SCI1CR1 4B Reset value SCI1CR2 4C ...
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ST72561-Auto 16 LINSCI serial communication interface (LIN master only) 16.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a ...
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LINSCI serial communication interface (LIN master only) 16.3 General description The interface is externally connected to another device by three pins (see block diagram). Any SCI bidirectional communication requires a minimum of two pins: Receive Data In (RDI) and Transmit ...
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ST72561-Auto Figure 88. SCI block diagram TDO RDI CLOCK EXTRACTION SCLK PHASE AND POLARITY SCICR2 TIE TCIE INTERRUPT CONTROL TRANSMITTER CLOCK f 16.4 Functional description The block diagram of the serial control interface, is shown in dedicated registers: ● Three ...
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LINSCI serial communication interface (LIN master only) Refer to the register descriptions in definitions of each bit. 16.4.1 Serial data format Word length may be selected as being either bits by programming the M bit in the ...
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ST72561-Auto Character transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Procedure ...
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LINSCI serial communication interface (LIN master only) Idle characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a transmission sends an idle frame ...