ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 229

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
17.4.5
Table 83.
Figure 104. CAN error state diagram
Error management
The error management as described in the CAN protocol is handled entirely by hardware
using a Transmit Error Counter (TECR register) and a Receive Error Counter (RECR
register), which get incremented or decremented according to the error condition. For
detailed information about TEC and REC management, please refer to the CAN standard.
Both of them may be read by software to determine the stability of the network.
Furthermore, the CAN hardware provides detailed information on the current error status in
CESR register. By means of CEIER register and ERRIE bit in CIER register, the software
can configure the interrupt generation on error detection in a very flexible way.
Bus-off recovery
The Bus-Off state is reached when TECR is greater then 255, this state is indicated by
BOFF bit in CESR register. In Bus-Off state, the beCAN acts as disconnected from the CAN
bus, hence it is no longer able to transmit and receive messages.
Depending on the ABOM bit in the CMCR register beCAN will recover from Bus-Off
(become error active again) either automatically or on software request. But in both cases
the beCAN has to wait at least for the recovery sequence specified in the CAN standard
(128 x 11 consecutive recessive bits monitored on CANRX).
Offset to receive mailbox base
address (bytes)
Receive mailbox mapping (continued)
When 128 * 11 recessive bits occur:
10
11
12
13
14
15
ERROR ACTIVE
Doc ID 12370 Rev 8
When TEC or REC > 127
When TEC and REC < 128,
BUS OFF
Register Name
Reserved
Reserved
ERROR PASSIVE
MDAR4
MDAR5
MDAR6
MDAR7
When TEC > 255
beCAN controller (beCAN)
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