ST72561J6-Auto STMicroelectronics, ST72561J6-Auto Datasheet - Page 149

• Manufacturer Part Number: ST72561J6-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72561J6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years at 55 °C
• 5 Power Saving Modes: halt, auto wake up from halt, active halt, wait and slow

ST72561-Auto
14.3.5
14.3.6
Note:
14.4
Note:
Note: The slave must have the same CPOL and CPHA settings as the master.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
2.
Slave mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
●
●
Clearing the SPIF bit is performed by the following software sequence:
1.
2.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see
(OVR)).
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (See
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 74
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
Write to the SPICSR register to perform the following actions:
–
–
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
The SPIF bit is set by hardware.
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
An access to the SPICSR register while the SPIF bit is set
A write or a read to the SPIDR register
Figure
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see
Manage the SS pin as described in
CPHA = 1 SS must be held low continuously. If CPHA = 0 SS must be held low
during byte transmission and pulled up between each byte to let the slave write in
the shift register.
shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
Figure
74).
74).
Doc ID 12370 Rev 8
Slave select management
Serial peripheral interface (SPI)
and
Overrun condition
Figure
72. If
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