ST92F150CV1 STMicroelectronics, ST92F150CV1 Datasheet - Page 125

• Manufacturer Part Number: ST92F150CV1
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST92F150CV1

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

6.6 DMA REGISTERS
As each peripheral DMA channel has its own spe-
cific control registers, the following register list
should be considered as a general example. The
names and register bit allocations shown here
may be different from those found in the peripheral
chapters.
DMA COUNTER POINTER REGISTER (DCPR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 7:1 = C[7:1]: DMA Transaction Counter Point-
er.
Software should write the pointer to the DMA
Transaction Counter in these bits.
Bit 0 = RM: Register File/Memory Selector.
This bit is set and cleared by software.
0: DMA transactions are with memory (see also
1: DMA transactions are with the Register File
GENERIC EXTERNAL PERIPHERAL INTER-
RUPT AND DMA CONTROL (IDCR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 5 = IP: Interrupt Pending.
This bit is set by hardware when the Trigger Event
occurs. It is cleared by hardware when the request
is acknowledged. It can be set/cleared by software
in order to generate/cancel a pending request.
0: No interrupt pending
1: Interrupt pending
Bit 4 = DM: DMA Request Mask.
This bit is set and cleared by software. It is also
cleared when the transaction counter reaches
zero (unless SWAP mode is active).
0: No DMA request is generated when IP is set.
1: DMA request is generated when IP is set
C7
DAPR.DP)
7
7
C6
C5
IP
DM
C4
ST92F124/F150/F250 - ON-CHIP DIRECT MEMORY ACCESS (DMA)
C3
IM
PRL2 PRL1 PRL0
C2
C1
RM
0
0
Bit 3 = IM: End of block Interrupt Mask.
This bit is set and cleared by software.
0: No End of block interrupt request is generated
1: End of Block interrupt is generated when IP is
Bit 2:0 = PRL[2:0]: Source Priority Level.
These bits are set and cleared by software. Refer
to Section 6.2 DMA PRIORITY LEVELS for a de-
scription of priority levels.
DMA ADDRESS POINTER REGISTER (DAPR)
Read/Write
Address set by Peripheral
Reset value: undefined
Bit 7:1 = A[7:1]: DMA Address Register(s) Pointer
Software should write the pointer to the DMA Ad-
dress Register(s) in these bits.
Bit 0 = PS: Memory Segment Pointer Selector:
This bit is set and cleared by software. It is only
meaningful if DCPR.RM=0.
0: The ISR register is used to extend the address
1: The DMASR register is used to extend the ad-
DM IM Meaning
1
1
0
0
PRL2 PRL1 PRL0 Source Priority Level
0
0
0
0
1
1
1
1
A7
when IP is set
set. DMA requests depend on the DM bit value
as shown in the table below.
of data transferred by DMA (see MMU chapter).
dress of data transferred by DMA (see MMU
chapter).
7
0
1
0
1
0
0
1
1
0
0
1
1
A6
A DMA request generated without End of Block
interrupt when IP=1
A DMA request generated with End of Block in-
terrupt when IP=1
No End of block interrupt or DMA request is
generated when IP=1
An End of block Interrupt is generated without
associated DMA request (not used)
0
1
0
1
0
1
0
1
A5
0 Highest
1
2
3
4
5
6
7 Lowest
A4
A3
A2
A1
125/429
PS
0
9