ST92F150CV1 STMicroelectronics, ST92F150CV1 Datasheet - Page 299

• Manufacturer Part Number: ST92F150CV1
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST92F150CV1

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
Note: After an MCU reset, the DMA requests of
the JBLPD have a higher priority than the interrupt
requests.
If the DMASUSP bit of the OPTIONS register is
set, while the ERROR and TLA flags are set, no
DMA transfer will be performed, allowing the re-
lavent interrupt routines to manage each condition
and, if necessary, disable the DMA transfer (Refer
to
Table 56. JBLPD internal priority levels
The user can program the most significant bits of
the interrupt vectors by writing the V[7:3] bits of the
IVR register. Starting from the value stored by the
user, the JBLPD sets the three least significant
bits of the IVR register to produce four interrupt
vectors that are associated with interrupt sources
as shown in
Table 57. JBLPD interrupt vectors
Interrupt Vector
V[7:3] 000b
V[7:3] 010b
V[7:3] 100b
V[7:3] 110b
Section 10.9.6 DMA
Priority Level
Higher
Lower
Table
57.
Interrupt Source
ERROR, TLA
RDRF, REOB
TRDY, TEOB
EODM, EOFM
Interrupt Source
ERROR, TLA
EODM, EOFM
RDRF, REOB
TRDY, TEOB
Features).
J1850 Byte Level Protocol Decoder (JBLPD)
Each interrupt source has a pending bit in the
STATUS register, except the DMA interrupt sourc-
es that have the interrupt pending bits located in
the PRLR register.
These bits are set by hardware when the corre-
sponding interrupt event occurs. An interrupt re-
quest is performed only if the related mask bits are
set in the IMR register and the JBLPD has priority.
The pending bits have to be reset by the user soft-
ware. Note that until the pending bits are set (while
the corresponding mask bits are set), the JBLPD
processes interrupt requests. So, if at the end of
an interrupt routine the related pending bit is not
reset, another interrupt request is performed.
To reset the pending bits, different actions have to
be done, depending on each bit: see the descrip-
tion of the STATUS and PRLR registers.
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