STE400P STMicroelectronics, STE400P Datasheet - Page 10

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STE400P

Manufacturer Part Number
STE400P
Description
STE400P - 4 PORT 10-100 FAST ETHERNET TRANSCEIVER - PHY DATASHEET
Manufacturer
STMicroelectronics
Datasheet
STE400P
7.0 REGISTERS AND DESCRIPTORS DESCRIPTION
There are 20 registers with 16 bits each supported for each port of the STE400P. This includes 9 basic registers
which are defined according to the clause 22 “Reconciliation Sub-layer and Media Independent Interface” and
clause 28 “Physical Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of
IEEE802.3u standard. In addition, there are 11 registers for advanced chip control and status information.
7.1 MII Management Interface
The STE400P is fully compliant with the IEEE 802.3u MII specifications.
7.2 Register List
Table 2. Register List
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Address
1Ch
1Dh
1Ah
1Bh
1Eh
00h
01h
02h
03h
04h
05h
06h
07h
08h
10h
11h
12h
13h
18h
19h
Reg. Index
PR10
PR12
PR13
PR14
PR15
PR16
PR17
PR18
PR19
PR11
PR0
PR1
PR2
PR3
PR4
PR5
RP6
PR7
PR8
PR9
NEXT PAGE Auto-Negotiation Next Page Transmit Register
100AUXCTL 100BaseX Auxiliary Control Register
100AUX SR 100BaseX Auxiliary Status Register
AUX MODE
LP NXT PG
AUX EGSR
100 RX EC
100 FCSC
AUX CSR
AUX MPR
AUX SSR
AUX M2
Control
PID LO
ANLPA
PID HI
Name
Status
ANA
ANE
INT
MII Control Register
MII Status Register
PHY Identifier (HI) Register
PHY Identifier (LO) Register
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Link Partner Next Page Transmit Register
100BaseX Receiver Error Counter
100BaseX False Carrier Sense Counter
Auxiliary Control/Status Register
AuxiliaryStatus Summary Register
Interrupt Register
Auxiliary Mode 2 Register
Auxiliary Error and General Status Register
Auxiliary Mode Register
Auxiliary Multiple PHY Register
Register Descriptions

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