STE400P STMicroelectronics, STE400P Datasheet - Page 9

• Manufacturer Part Number: STE400P
• Description: STE400P - 4 PORT 10-100 FAST ETHERNET TRANSCEIVER - PHY DATASHEET
• Manufacturer: STMicroelectronics

STE400P
6.0 OPERATIONAL DESCRIPTION
6.1 Resetting the STE400P
There are two ways to reset each transceiver in the STE400P. A hardware reset pin has been provided which
resets all internal nodes inside the chip to a known state. The reset pulse must be asserted for at least 400 ns.
Hardware reset should always be applied to a STE400P after power-up.
Each transceiver also has an individual software reset capability. To perform software reset, a “1’ must be writ-
ten to bit 15 of the transceiver’s MII Control Register. This bit is self-clearing, i.e. that a second write operation
is not necessary to end the reset. There is no effect if a “0” is written to the MII Control Register reset bit.
6.2 Isolate Mode
Each transceiver in the STE400P may be isolated from the MII. When a transceiver is put into isolate mode, all
MII inputs are ignored, and all MII outputs are set at high impedance. Only the MII management pins operate
normally. Upon resetting the chip, the isolate mode is off. Writing a “1” to bit 10 of the MII Control Register puts
the transceiver into isolate mode. Writing a “0” to the same bit removes it from isolate mode.
6.3 Loopback Mode
The loopback mode allows in-circuit testing of the STE400P chip. All packets sent in through the TXD pins are
looped-back internally to the RXD pins, and are not sent out to the cable. Incoming packets on the cable are
ignored. Because of this, the COL pin will normally not be activated during loopback mode. In order to test that
the COL pin is actually working, the STE400P may be placed into collision test mode. This mode is enabled by
writing a “1” to bit 7 of the MII Control Register. Asserting TXEN will cause the COL output to go high and deas-
serting TXEn will cause the COL output to go low.
The loopback mode may be entered by writing a “1” to bit 14 of the MII Control Register. In order to resume
normal operation, bit 14 of the MII Control Register must be “0”.
Several function bypass modes are also supported which can provide a number of different combinations of
feedback paths during loopback testing. These bypass modes include: bypass scrambler, bypass MLT3 encod-
er and bypass 4B5B encoder.
6.4 Full Duplex Mode
The STE400P supports full duplex operation. While in full-duplex mode, a transceiver may simultaneously trans-
mit and receive packets on the cable. The COL signal is never activated while in full-duplex mode. By default,
each transceiver in the STE400P powers up in half-duplex mode.
When Auto Negotiation is disabled, full duplex operation can be enabled either by a pin (FDXEN) or by an MII
register bit (Register “0” bit 8). When Auto Negotiation is enabled in DTE mode, full-duplex capability is adver-
tised by default but can be overridden by a write to the Auto-Negotiation Advertisement Register (04h).
6.5 100BASE-T MODE
The same magnetics module is used to interface the twisted-pair cable in 10BASE-T mode and in 100BASE-
TX mode. The data will be two-level Manchester coded instead of three level MLT3 and no scrambling/descram-
bling or 4B5B coding is performed. Data and clock rates are decreased by a factor of 10, with the NII interface
operating at 2.5 MHz.
Each transceiver in the STE400P will have a unique PHY address for MII management. THe addresses will be
set through the PHY address pins. The pins are latched at the trailing end of reset. Transceiver 1 will have the
address AAA00 where AAA=PHYAD4, PHYAD3, PHYAD2. Transceivers 2 - 4 will have addresses AAA01,
AAA10 and AAA11, respectively.
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