STE400P STMicroelectronics, STE400P Datasheet - Page 6

• Manufacturer Part Number: STE400P
• Description: STE400P - 4 PORT 10-100 FAST ETHERNET TRANSCEIVER - PHY DATASHEET
• Manufacturer: STMicroelectronics

STE400P
6/34
Table 1. Pin Description
MODE
Pin.
204
185
177
158
202
183
179
160
201
182
180
161
104
105
42
38
39
40
SP100LED# {1}
SP100LED# {2}
SP100LED# {3}
SP100LED# {4}
LC Ser SCLK#
Ser SCLK# {2}
RCVLED# {2}
RCVLED# {3}
LC Ser SDO#
RCVLED# {4}
FDXLED# {1}
FDXLED# {2}
FDXLED# {3}
FDXLED# {4}
ACTLED# {2}
ACTLED# {3}
ACTLED# {4}
XMTLED#{1}
XMTLED#{2}
XMTLED#{3}
XMTLED#{4}
RCVLED#{1}
ACTLED {1}
Ser SDO#
INTR# {1}
INTR# {2}
INTR# {3}
INTR# {4}
PHYAD4
PHYAD3
PHYAD2
FDXEN
Name
ANEN
F100
Type
Ood
Ood
Ipd
Ipd
Ipu
Ipu
O
Speed 100 LED: Driven low when operating in 100BASE-X modes and high
when operating in 10BASE-T modes
Transmit Activity LED: Active low output. The transmit activity LED is driven
low for approximately 80ms each time there is transmit activity while in the
link pass state. When INTR mode is enable, the pin becomes an interrupt
output. When FDX LED mode is enabled, the pin becomes FDXLED output.
When the Serial LED mode is enabled, pin 183 becomes the Serial LED
mode data output signal.
Receive Activity LED: Active low output. The receive activity LED is
driven low for approximately 80ms each time there is receive activity
while in the link pass state. When in either INTR or FDXLED modes, this
pin becomes ACTLED output for either receive or transmit activity.
When the Serial LED mode is enabled, pin 182 becomes the Serial LED
mode clock signal. When the low cost serial LED mode is enabled, pin
201 becomes Low cost serial LED mode clock signal and pin 180 be-
comes the data output signal.
Full-Duplex Enable.
When A/N is enabled, FDE determines full-duplex advertisement capa-
bility in combination with CFG0 and CFG1. (See Table 2)
When A/N is disabled, FDE directly affects full-duplex operation and de-
termines the value of PR0 bit 8 (Full/Half Duplex Mode Select).
PHY Address Selects: These inputs set the three MSB’s for the MII
management PHY addresses. THe two LSB’s, PHYAD1, PHYAD0 are
internally wired to each of the four ports: PHYAD[00] = Port1,.., PHYAD[11] =
Port4.
Force 100BASE-X Operation: When F100 is high and ANEN is low, all
transceivers will be forced to 100BASE-X operation. When F100 is low and
ANEN is low, all transceivers are forced to 10BASE-T operation. When
ANEN is high, F100 has no effect on operation
Auto Negotiation Enable: When pulled high, Auto-Negotiation begins
immediately after reset. When low, it is disabled after reset.
Description