STE400P STMicroelectronics, STE400P Datasheet - Page 7

• Manufacturer Part Number: STE400P
• Description: STE400P - 4 PORT 10-100 FAST ETHERNET TRANSCEIVER - PHY DATASHEET
• Manufacturer: STMicroelectronics

Table 1. Pin Description
BIAS
JTAG
101
102
103
44
Power
181
7
8
77
Pin.
125
100
116
115
43
54
53
78
79
99
INTR/clk_20lbk
NANDMD1
NANDMD0
BIASVDD
DLLTEST
PLLGND
TESTEN
PLLVDD
TRST#
RDAC
Name
VREF
IVDD
TDO
TMS
TCK
ER1
ER0
TDI
I/Opd
Type
O3s
Ipu
Ipd
Ipd
Ipu
Ipu
Ipu
Ipu
Ipu
B
B
Transmit DAC Edge Rate Control: These pins control the slew rate of each of
the transmit DAC’s.
Test Enable: Active-high test control inputs used along with NANDMD1, 0
and PHYAD[4:2] to select the NAND-chain test mode. Both inputs must be
driven high
during latching of test mode. Must be pulled low or left unconnected during
normal operation.
NAND Mode: Active-high test control inputs used along with TESTEN and
PHYAD[4:2} to select the NAND-chain test mode. Both inputs must be driven
high during latching of the test mode. Must be kept at low or left unconnected
during normal operation.
Bidirectional pad : input - clk_20lbk used to bypass internal 20 MHz PLL,
output - intr as per interrupt register.
DAC Bias Resistor: A 5K ohm + - 1% resistor must be connected between
this pin and AGND for normal operation.
Voltage Reference: Low-impedance bias pin driven by the internal bandgap
voltage reference. This pin must be left unconnected during normal
operation.
Test Data Input: Serial data input to the JTAG TAP controller. Sampled on the
rising edge of TCK. If unused, may be left unconnected
Test Data Output: Serial data output from the JTAG TAP controller. Updated
on the falling edge of TCK. Actively driven both high and low when enabled.
Test Mode Select: Single control input to the JTAG TAP Controller used to
traverse the test-logic state machine. Sampled on the rising edge of TCK. If
unused, may be left unconnected
Test Clock: Clock input used to synchronize JTAG control and data transfers.
If unused, may be left unconnected
Test Reset: Asynchronous active-low reset input to the JTAG TAP controller.
Must be held low during power up to insure the TAP controller initializes to
the test-logic-reset state. May be pulled low continuously when JTAG
functions are not used
DLL Bypass Test Enable: This pin is for factory test only and must be
connected to DVDD or left floating
Input VDD: +5.0V or +3.3V. If any of the inputs are driven to 5.0V, this pin
must be connected to the 5.0V supply. If none of the inputs are driven above
3.3V, this pin may be connected to the 3.3V supply
Phase Locked Loop VDD
Phase Locked Loop GND
Bias VDD
Description
STE400P
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