XA-G39 NXP Semiconductors, XA-G39 Datasheet - Page 33

• Manufacturer Part Number: XA-G39
• Description: Xa 16-bit Microcontroller Family Xa 16-bit Microcontroller 32k Flash/1k Ram, Watchdog, 2 Uarts
• Manufacturer: NXP Semiconductors

1. Load capacitance for all outputs = 80pF.
2. Variables V1 through V13 reflect programmable bus timing, which is programmed via the Bus Timing registers (BTRH and BTRL).
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (5 V)
V
NOTES:
2002 Mar 13
External Clock
Address Cycle
Code Read Cycle
Data Read Cycle
Data Write Cycle
Wait Input
DD
SYMBOL
SYMBOL
XA 16-bit microcontroller family
32K Flash/1K RAM, watchdog, 2 UARTs
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
C
CHCX
CLCX
CLCH
CHCL
CRAR
LHLL
AVLL
LLAX
PLPH
LLPL
AVIVA
AVIVB
PLIV
PXIX
PXIZ
IXUA
RLRH
LLRL
AVDVA
AVDVB
RLDV
RHDX
RHDZ
DXUA
WLWH
LLWL
QVWX
WHQX
AVWL
UAWH
WTH
WTL
Refer to the XA User Guide for details of the bus timing settings.
V1)
= 4.5 V to 5.5 V; T
V1 = 0.5 if the ALEW bit = 0, and 1.5 if the ALEW bit = 1.
This variable represents the programmed width of the ALE pulse as determined by the ALEW bit in the BTRL register.
FIGURE
FIGURE
26
26
26
26
26
25
20
20
20
20
20
20
21
20
20
20
20
22
22
22
23
22
22
22
22
24
24
24
24
24
24
25
25
amb
= 0 to +70 C for commercial; V
Oscillator frequency
Clock period and CPU timing cycle
Clock high time
Clock low time
Clock rise time
Clock fall time
Delay from clock rising edge to ALE rising edge
ALE pulse width (programmable)
Address valid to ALE de-asserted (set-up)
Address hold after ALE de-asserted
PSEN pulse width
ALE de-asserted to PSEN asserted
Address valid to instruction valid, ALE cycle (access time)
Address valid to instruction valid, non-ALE cycle (access time)
PSEN asserted to instruction valid (enable time)
Instruction hold after PSEN de-asserted
Bus 3-State after PSEN de-asserted (disable time)
Hold time of unlatched part of address after instruction latched
RD pulse width
ALE de-asserted to RD asserted
Address valid to data input valid, ALE cycle (access time)
Address valid to data input valid, non-ALE cycle (access time)
RD low to valid data in, enable time
Data hold time after RD de-asserted
Bus 3-State after RD de-asserted (disable time)
Hold time of unlatched part of address after data latched
WR pulse width
ALE falling edge to WR asserted
Data valid before WR asserted (data setup time)
Data hold time after WR de-asserted (Note 6)
Address valid to WR asserted (address setup time) (Note 5)
Hold time of unlatched part of address after WR is de-asserted
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
WAIT hold after bus strobe (RD, WR, or PSEN) assertion
PARAMETER
PARAMETER
DD
= 4.75 V to 5.25 V, –40 C to +85 C for industrial.
33
(V12 * t
(V13 * t
(V1 * t
(V2 * t
(V7 * t
(V8 * t
(V9 * t
(V10 * t
(V11 * t
(V11 * t
(V1 * t
(t
(t
(t
t
t
C
C
C
C
C
/2) – 10
MIN
1/f
* 0.5
* 0.4
/2) – 7
/2) – 7
VARIABLE CLOCK
0
5
0
0
0
0
C
C
C
C
C
C
C
C
C
C
C
) – 14
) – 10
) – 10
) – 10
) – 22
C
) – 6
) – 10
) – 22
) – 7
) – 7
) – 5
7
7
(V10 * t
(V3 * t
(V4 * t
(V2 * t
(V6 * t
(V5 * t
(V7 * t
t
t
MAX
C
C
30
46
5
5
C
C
C
– 8
C
C
C
– 8
C
) – 36
) – 29
) – 29
) – 36
) – 29
) – 29
) – 30
XA-G39
Preliminary data
UNIT
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns