ACS8514 Semtech Corporation, ACS8514 Datasheet - Page 29

• Manufacturer Part Number: ACS8514
• Description: Synchronous Equipment Timing Source Partner IC for 2nd T4 Dpll, Accurate Monitoring & Input Extender
• Manufacturer: Semtech Corporation

Each Register, or register group, is described in the
following
Description Tables.
Register Organization
The ACS8514 SETS uses a total of 104 8-bit registers,
identified by a Register Name and corresponding
hexadecimal Register Address. They are presented here in
ascending order of Reg. address and each Register is
organized with the most-significant bit positioned in the
left-most bit, and bit significance decreasing towards the
right-most bit. Some registers carry several individual data
fields of various sizes, from single-bit values (e.g. flags)
upwards. Several data fields are spread across multiple
registers, as shown in the Register Map. Shaded areas in
the map are "don't care" and writing either 0 or 1 will not
affect any function of the device. Bits labeled "Set to zero"
or "Set to one" must be set as stated during initialization
of the device, either following power- up, or after a Power-
On Reset (POR). Failure to correctly set these bits may
result in the device operating in an unexpected way.
CAUTION! Do not write to any undefined register addresses
as this may cause the device to operate in a test mode. If
an undefined register has been inadvertently addressed,
the device should be reset to ensure the undefined
registers are at default values.
Multi-word Registers
For Multi-word Registers (e.g. register 0C & 0D), all the
words have to be written to their separate addresses, and
without any other access taking place, before their
combined value can take effect. If the sequence is
interrupted, the sequence of writes will be ignored.
Reading a multi-word address freezes the other address
words of a multi-word address so that the bytes all
correspond to the same complete word.
Register Access
Most registers are of one of two types, configuration
registers or status registers, the exceptions being the
chip_id register (addr. 00) and chip_revision registers
(addr. 02). Configuration registers may be written to or
read from at any time (the complete 8-bit register must be
written, even if only one bit is being modified). All status
registers may be read at any time and, in some status
registers (such as the sts_interrupts register), any
individual data field may be cleared by writing a 1 into
Revision 3.00 April 2007 © Semtech Corp.
Register Map
ADVANCED COMMS & SENSING
Register
Map
and
subsequent
Register
Page 29
FINAL
each bit of the field (writing a 0 value into a bit will not
affect the value of the bit). A description of each register is
given in the Register Map, and Register Map Description.
Configuration Registers
Each configuration register reverts to a default value on
power-up or following a reset. Most default values are
fixed, but some will be pin-settable. All configuration
registers can be read out over the microprocessor port.
Status Registers
The Status Registers contain readable registers. They may
all be read from outside the chip but are not writeable
from outside the chip (except for a clearing operation). All
status registers are read via shadow registers to avoid
data hits due to dynamic operation. Each individual status
register has a unique location.
Interrupt Enable and Clear
Interrupt requests are flagged on pin INTREQ; the active
state (High or Low) is programmable and the pin can
either be driven, or set to high impedance when non-active
(Reg 7D refers). Bits in the interrupt status register are set
(High) by the following conditions;
1. Any reference source becoming valid or going invalid.
2. A change in the operating state (e.g. Locked, Holdover etc.)
3. A brief loss of the currently selected reference source.
4. An AMI input error.
All interrupt sources (see register 05, 06 & 08) are
maskable via the mask register, each one being enabled by
writing a 1 to the appropriate bit. Any unmasked bit set in
the interrupt status register will cause the interrupt request
pin to be asserted. All interrupts are cleared by writing a 1
to the bit(s) to be cleared in the status register. When all
pending unmasked interrupts are cleared the interrupt pin
will go inactive.
Defaults
Each Register is given a defined default value at reset and
these are listed in the Map and Description Tables.
However, some read-only status registers may not
necessarily show the same default values after reset as
those given in the tables. This is because they reflect the
status of the device which may have changed in the time it
takes to carry out the read, or through reasons of
configuration. In the same way, the default values given
for shaded areas could also take different values to those
stated.
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