ACS8514 Semtech Corporation, ACS8514 Datasheet - Page 50

• Manufacturer Part Number: ACS8514
• Description: Synchronous Equipment Timing Source Partner IC for 2nd T4 Dpll, Accurate Monitoring & Input Extender
• Manufacturer: Semtech Corporation

Revision 3.00 April 2007 © Semtech Corp.
Address(hex): 41
Address(hex): 42
Address(hex): 43
Register Name
Register Name cnfg_DPLL_freq_limit
Register Name
I8
ADVANCED COMMS & SENSING
Bit No.
Bit No.
Bit No.
Bit 7
[7:2]
[1:0]
Bit 7
[7:0]
Bit 7
7
6
5
[9:8]
Description
Not used.
DPLL_freq_limit_value[9:8]
cnfg_DPLL_freq_limit
[7:0]
Description
DPLL_freq_limit_value[7:0]
This register defines the extent of frequency offset
to which either the Monitor or the T4 DPLL will track
a source before limiting- i.e. it represents the pull-in
range of the DPLLs. The offset of the device is
determined by the frequency offset of the DPLL
when compared to the offset of the external crystal
oscillator clocking the device. If the oscillator is
calibrated using register 3C & 3D, then this
calibration is automatically taken into account. The
DPLL frequency limit limits the offset of the DPLL
when compared to the calibrated oscillator
frequency.
cnfg_interrupt_mask
[7:0]
I7
Description
I8
Mask bit for input I8 interrupt.
I7
Mask bit for input I7 interrupt.
I6
Mask bit for input I6 interrupt.
Bit 6
Bit 6
Bit 6
Bit 5
I6
Bit 5
Description (R/W) Bits [9:8] of the DPLL frequency limit register.
Bit 5
Description
I5
Bit 4
Bit 4
Description
DPLL_freq_limit_value[7:0]
(R/W) Bits [7:0] of the interrupt mask register.
I4
Bit 4
Bit Value
Page 50
FINAL
Bit 3
-
-
Bit Value
Bit 3
(R/W) Bits [7:0] of the DPLL
frequency limit register.
0
1
0
1
0
1
Bit Value
Bit 3
-
Value Description
-
See register 41 (cnfg_DPLL_freq_limit.) for details.
I3
Value Description
Input I8 cannot generate interrupts.
Input I8 can generate interrupts.
Input I7 cannot generate interrupts.
Input I7 can generate interrupts.
Input I6 cannot generate interrupts.
Input I6 can generate interrupts.
Value Description
In order to calculate the frequency limit in ppm,
bits[1:0] of register 42h & bits[7:0] of register
41h need to be concatenated. This value is a
unsigned integer and represents the limit, both
positive and negative, in ppm. The value
multiplied by 0.078 will give the value in ppm.
Bit 2
ACS8514 SETS Buddy
Bit 2
Bit 2
Default Value
Default Value
Default Value
I2
DPLL_freq_limit_value[9:8]
Bit 1
Bit 1
Bit 1
DATASHEET
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0111 0110
0000 0000
0000 0000
I1
Bit 0
Bit 0
Bit 0