ACS8514 Semtech Corporation, ACS8514 Datasheet - Page 69

• Manufacturer Part Number: ACS8514
• Description: Synchronous Equipment Timing Source Partner IC for 2nd T4 Dpll, Accurate Monitoring & Input Extender
• Manufacturer: Semtech Corporation

Revision 3.00 April 2007 © Semtech Corp.
Address(hex): 74
Register Name
coarse_lim-
phaseloss_en
ADVANCED COMMS & SENSING
Bit No.
Bit 7
[3:0]
7
6
5
4
cnfg_phase_loss_coarse_limit
wide_range_en
Description
coarse_lim_phaseloss_en
Register bit to enable the coarse phase detector, whose range is
determined by phase_loss_coarse_limit Bits [3:0]. This register
sets the limit in the number of input clock cycles (UI) that the
input phase can move by before the DPLL indicates phase lost.
wide_range_en
To enable the device to be tolerant to large amounts of applied
jitter and still do direct phase locking at the input frequency rate
(up to 77.76 MHz), a wide range phase detector and phase lock
detector is employed. This bit enables the wide range phase
detector. This allows the device to be tolerant to, and therefore
keep track of, drifts in input phase of many cycles (UI). The range
of the phase detector is set by the same register used for the
phase loss coarse limit (Bits [3:0]).
multi_ph_resp
Enables the phase result from the coarse phase detector to be
used in the DPLL algorithm. Bit 6 should also be set when this is
activated. The coarse phase detector can measure and keep
track over many thousands of input cycles, thus allowing
excellent jitter and wander tolerance. This bit enables that phase
result to be used in the DPLL algorithm, so that a large phase
measurement gives a faster pull-in of the DPLL. If this bit is not
set then the phase measurement is limited to ±360º which can
give a slower pull-in rate at higher input frequencies, but could
also be used to give less overshoot.
Setting this bit in direct locking mode, for example
with a 19.44 MHz input, could be used to give the same dynamic
response as a 19.44 MHz input used with 8 k locking mode,
where the input is divided down internally to 8 kHz first.
Not used.
phase_loss_coarse_limit
Sets the range of the coarse phase loss detector and the coarse
phase detector.
When locking to a high frequency signal and jitter tolerance
greater than ± 0.5 UI is required, then the DPLL can be
configured to track phase errors over many input clock periods.
This is particularly useful with very low bandwidths. This register
configures how many UI over which the input phase can be
tracked. It also sets the range of the coarse phase loss detector,
which can be used with or without the multi-UI phase capture
range capability.
This register value is used by Bits 6 and 7.
Bit 6
multi_ph_resp
Bit 5
Description
Bit 4
Page 69
FINAL
(R/W) Register to configure some
of the parameters of the Monitor
DPLL phase detector.
Bit 3
Bit Value Value Description
1100-
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1111
0
1
0
1
0
1
-
phase_loss_coarse_limit
ACS8514 SETS Buddy
Bit 2
Phase loss not triggered by the coarse
phase lock detector.
Phase loss triggered when phase error
exceeds the limit programmed in
phase_loss_coarse_limit , Bits [3:0].
Wide range phase detector off.
Wide range phase detector on.
DPLL phase detector limited to ±360º (±1
UI). However it will still remember its
original phase position over many
thousands of UI if Bit 6 is set.
DPLL phase detector also uses the full
coarse phase detector result. It can now
measure up to:
±360º X 8191 UI = ±2,948,760º.
-
Input phase error tracked over ±1 UI.
Input phase error tracked over ±3 UI.
Input phase error tracked over ±7 UI.
Input phase error tracked over ±15 UI.
Input phase error tracked over ±31 UI.
Input phase error tracked over ±63 UI.
Input phase error tracked over ±127 UI.
Input phase error tracked over ±255 UI.
Input phase error tracked over ±511 UI.
Input phase error tracked over ±1023 UI.
Input phase error tracked over ±2047 UI.
Input phase error tracked over ±4095 UI.
Input phase error tracked over ±8191 UI.
Default Value
Bit 1
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1000 0101
Bit 0