ACS8514 Semtech Corporation, ACS8514 Datasheet - Page 7

• Manufacturer Part Number: ACS8514
• Description: Synchronous Equipment Timing Source Partner IC for 2nd T4 Dpll, Accurate Monitoring & Input Extender
• Manufacturer: Semtech Corporation

The ACS8514 is a highly integrated multiple phase lock
loop device designed to partner the ACS8530 and
ACS8520 SETS (Synchronous Equipment Timing Source)
ICs. It specifically provides one additional BITS / T4 Path
to allow a complete clock synchronization system to have
two totally independent T4 paths and one T0 path, for
those systems constructed to exactly match the
configuration as defined in GR253 figure 5-21.
The electrical interfaces for input clocks, configurations
and micro-processor interfaces are identical to the
ACS8520/30. This allows the same processor interface
pins to be shared with this part, with the correct part
accessed by using a separate chip select.
All 14 input clocks and the 12.8 MHz TCXO/OCXO system
clock can also be shared via parallel connections.
An alternative use for this part is as an input extender for
those systems requiring a selection of more than 14
inputs, or more inputs of a particular electrical interface
type. The 14 in-built activity monitors and frequency
monitors can automatically qualify an input clock and
select that clock based on a preset priority. The T4 DPLL
output can then be fed on to the ACS8520/30 for
subsequent selection according to its priority tables, as
required.
The third main set of functions that this part brings to a
system is the capability to very precisely measure
the phase and frequency at the inputs. Another
independently controlled ‘monitor DPLL’ can be used for
this function. This precise measurement capability can
measure phase to a 0.7 degrees accuracy with a range up
to 23000º degrees and frequency to 0.3 parts per billion
(3 x 10
coarse frequency monitoring that occurs simultaneously
on each of the 14 input pins to a 3.9 ppm frequency
accuracy. The measured phase values may be used to
give a TIE (Time Interval Error), MTIE (Maximum TIE) and
TDEV (Time Deviation) quality assessment of each input
using appropriate external software. The phase and
frequency measurement DPLL, the Monitor DPLL, can be
set to a range of loop bandwidths, down to 0.5 mHz. The
phase of an input is measured with respect to the Monitor
DPLL output, so varying the DPLL’s bandwidth has the
effect of changing the maximum observation time for the
TIE measurements. A TIE observation period of up to
approximately 2000 seconds is allowed for with the 0.5 mHz
bandwidth.
Revision 3.00 April 2007 © Semtech Corp.
Introduction
ADVANCED COMMS & SENSING
-10
), this is in addition to the activity monitoring and
FINAL
Page 7
Longer observation time measurements of TIE, MTIE and
TDEV can be made by using the T4 DPLL since the T4
phase detectors can be configured to measure the phase
difference between two independent inputs. This means
that there is no limit to the maximum observation time
that can be measured.
A Digital Phase Locked Loop (DPLL) incorporating direct
digital synthesis (DDS) is used in the device in order to
perform frequency translation. This enables the ACS8514
to have overall PLL characteristics that are very stable and
consistent, compared to traditional analog PLLs.
In the absence of any input clock after power up the
ACS8514 will free-run and generate a stable, low-noise
clock signal at a frequency to the same accuracy as the
external 12.8 MHz TCXO or OCXO, or it can be made more
accurate via software calibration to 0.02 ppm.
Once an input clock source becomes available and is
measured and found to be of a good quality, the T4 DPLL
will lock to the source with the highest priority (number 1
is the highest priority in the priority table). If all sources
subsequently fail then either the last source frequency is
held on the T4 DPLL output (holdover) or the output may
be automatically turned off (squelched) depending on
configuration.
An internal analog PLL (APLL) is used in the feedback path
of the DPLLs in order to eliminate digital sampling effect
uncertainty at the DPLL PFDs (Phase and Frequency
Detectors).
The ACS8514 includes a multi-standard microprocessor
port, providing access to the configuration and status
registers for device setup and monitoring.
Overview
The following description refers to the Block Diagram
(Figure 1 on page 1).
The ACS8514 SETS device has 14 input clocks and
generates 2 output clocks derived from the T4 DPLL path.
Of the 14 input references, two are AMI composite clock,
two are LVDS/PECL and the remaining ten are TTL/CMOS
compatible inputs. All the TTL/CMOS are 3 V and 5 V
compatible (with clamping if required by connecting the
VDD5 pin). The AMI inputs are ±1 V typically, A.C. coupled.
Refer to the electrical characteristics section for more
information on the electrical compatibility and details.
Input frequencies supported range from 2 kHz to 155.52
MHz.
General Description
ACS8514 SETS Buddy
DATASHEET
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