ACS8514 Semtech Corporation, ACS8514 Datasheet - Page 36

• Manufacturer Part Number: ACS8514
• Description: Synchronous Equipment Timing Source Partner IC for 2nd T4 Dpll, Accurate Monitoring & Input Extender
• Manufacturer: Semtech Corporation

Revision 3.00 April 2007 © Semtech Corp.
Address(hex):
Address(hex): 09
Register Name
ADVANCED COMMS & SENSING
7, 3, 2, 1, 0
Bit No.
Bit No.
Bit 7
2
1
0
6
Description
AMI2_LOS
Interrupt indicating that an AMI LOS error has
occurred on input I2. Latched until reset by software
writing a 1 to this bit.
AMI1_Viol
Interrupt indicating that an AMI Violation error has
occurred on input I1. Latched until reset by software
writing a 1 to this bit.
AMI1_LOS
Interrupt indicating that an AMI LOS error has
occurred on input I1. Latched until reset by software
writing a 1 to this bit.
sts_operating
T4_DPLL_Lock Mon_DPLL_freq
Description
Not used
T4_DPLL_Lock
The bit indicates that the T4 DPLL is locked by
monitoring the T4DPLL phase loss indicators, which
potentially come from four sources. The four phase
loss indicators are enabled by the same registers
that enable them for the Monitor DPLL, as follows:
the fine phase loss detector enabled by register 73
bit 7, the coarse phase loss detector enabled by
register 74 bit 7, the phase loss indication from no
activity on the input enabled by register 73 bit 6 and
phase loss from the DPLL being at its min or max
frequency limits enabled by register 4D bit 7.
For this T4_DPLL_lock indication this bit will latch an
indication of phase lost from the coarse phase lock
detector such that when an indication of phase lost
(or not locked) is set it stays in that phase lost or not
locked state (so this bit = 0).
Since this bit latches the indication of phase lost
from the coarse phase loss detector, then for this bit
to give a correct current reading of the T4 DPLL
locked state, then the coarse phase loss detector
should be temporarily disabled (register 74, bit 7 =
0), then the T4_DPLL_lock bit can be read, then the
coarse phase loss detector should be re-enabled
again (register 74, bit7=1).
08
Bit 6
(continued)
_soft_alarm
Bit 5
Description
T4_DPLL_freq_
soft_alarm
Bit 4
Page 36
FINAL
(RO) Current operating state of
the internal DPLL’s.
Bit Value
Bit Value
Bit 3
0
1
0
1
0
1
0
1
-
Value Description
Input I2 has had no LOS error.
Input I2 has had a LOS error.
Writing 1 resets the input to 0.
Input I1 has had no violation error.
Input I1 has had a violation error.
Writing 1 resets the input to 0.
Input I1 has had no LOS error.
Input I1 has had a LOS error.
Writing 1 resets the input to 0.
Value Description
-
T4 DPLL not phase locked to reference source.
T4 DPLL phase locked to reference source.
Once this bit is indicating 'locked' (=1), it is
always a correct indication and no change to the
coarse phase loss detector enable is required. If
at any time any cycle slips occur that trigger the
coarse phase loss detector (which monitors
cycle slips) then this information is latched so
that the lock bit (reg 09, bit 6) will go low and
stay low, indicating that a problem has occurred.
It is then a requirement that the coarse phase
loss detector disable / re-enable sequence is
performed during a read of the T4 locked bit, in
order to get a current indication of whether the
T4 DPLL is locked.
It is recommended that register 73 bit 6 is set to
‘1’ so that no activity on the input sets phase
lost and hence sets T4_DPLL_Lock = 0 ,
otherwise a locked indication can be indicated in
the case of no input clock, since all other phase
loss indicators are in a holding state. Register
73, bit 6 = 1 avoids this case and gives correct
lock indication.
ACS8514 SETS Buddy
Bit 2
Default Value
Bit 1
DATASHEET
www.semtech.com
0100 0001
Bit 0