ACS8514 Semtech Corporation, ACS8514 Datasheet - Page 8

• Manufacturer Part Number: ACS8514
• Description: Synchronous Equipment Timing Source Partner IC for 2nd T4 Dpll, Accurate Monitoring & Input Extender
• Manufacturer: Semtech Corporation

Common E1, DS1, OC3 and sub-divisions are supported
as spot frequencies that the DPLLs will directly lock to. Any
input frequency, up to 100 MHz, that is a multiple of 8
kHz, can also be locked to via an inbuilt programmable
divider.
An input reference monitor is assigned to each of the 14
inputs. The monitors operate continuously such that at all
times the status of all of the inputs to the device is known.
Each input can be monitored for both frequency and
activity, activity alone, or the monitors can be disabled.
The frequency monitors have a "hard" (rejection) alarm
limit and a "soft" (flag only) alarm limit for monitoring
frequency. Each input reference can be programmed with
a priority number allowing references to be chosen
according to the highest priority valid input. The input
selection can operate in either automatic mode or external
manual source selection mode.
The T4 PLL path supports the following features:
Either external software or an internal state machine
controls the T4 DPLL source selection based on input
quality and priority.
Revision 3.00 April 2007 © Semtech Corp.
ADVANCED COMMS & SENSING
Automatic source selection according to input priorities
and quality level.
Different quality levels (activity alarm thresholds) for
each input
Variable bandwidth (18, 35 or 70 Hz), lock range (0 –
80 ppm) and damping factor.
Direct PLL locking to common SONET/SDH input
frequencies or any multiple of 8 kHz
Automatic locking to an available source and either
squelch or holdover mode when no source.
Fast detection on input failure.
Output holds last frequency (holdover) or output
squelch when all input sources failed.
Frequency translation between input and output rates
via direct digital synthesis
High accuracy digital architecture for stable PLL
dynamics..
Ability to measure a phase difference between two
inputs.
Analog PLL (APLL) used in the feedback path to avoid
digital sampling / aliasing effects.
FINAL
Page 8
Input Reference Clock Ports
Table 4 gives details of the input reference ports, showing
the input technologies and the range of frequencies
supported on each port; the default spot frequencies and
default priorities assigned to each port on power-up or by
reset are also shown. Note that SDH and SONET networks
use different default frequencies; the network type is pin-
selectable (using either the SONSDHB pin or via software).
Specific
configuration.
SDH and SONET networks use different default frequencies;
the network type is selectable using the register bit
ip_sonsdhb, at address 34, bit 2.
On power-up or by reset, the default will be set by the
state of the SONSDHB pin (pin 100).
The specific frequency selection is programmed via the
cnfg_ref_source registers (addresses 22 to 2D).
Locking Frequency Modes
There are three locking frequency modes that can be
configured: Direct Lock, Lock 8k and DivN.
Direct Lock Mode
In Direct Lock Mode, the internal DPLL can lock to the
selected input at the spot frequency of the input, for
example
comparisons at 19.44 MHz.
In Lock8K and DivN modes (and for special case of 155
MHz), an internal divider is used prior to the DPLL to
divide the input frequency before it is used for phase
comparisons in the DPLL.
Lock8K Mode
Lock8K mode automatically sets the divider parameters to
divide the input frequency down to 8 kHz. Lock8K can only
be used on the supported spot frequencies (see Table 1,
note 0). Lock8k mode is enabled by setting the Lock8k bit
(Bit 6) in the appropriate register location (at address 22
to 2D). Using lower frequencies for phase comparisons in
the DPLL results in a greater tolerance to input jitter. It is
possible to choose which edge of the input reference clock
to lock to, by setting 8K edge polarity (Bit 2 of register 03).
For SONET, ip_sonsdhb = 1
For SDH, ip_sonsdhb = 0
frequencies
19.44
MHz
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