AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 268

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AT90CAN128-16AE

Manufacturer Part Number
AT90CAN128-16AE
Description
8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
Manufacturer
ATMEL Corporation
Datasheet
Differential Channels
268
AT90CAN128
Figure 129. ADC Timing Diagram, Auto Triggered Conversion
Figure 130. ADC Timing Diagram, Free Running Conversion
Table 98. ADC Conversion Time
When using differential channels, certain aspects of the conversion need to be taken
into consideration.
Differential conversions are synchronized to the internal clock CK
ADC clock frequency. This synchronization is done automatically by the ADC interface
in such a way that the sample-and-hold occurs at a specific phase of CK
sion initiated by the user (i.e., all single conversions, and the first free running
conversion) when CK
conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion ini-
tiated by the user when CK
synchronization mechanism. In Free Running mode, a new conversion is initiated imme-
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Condition
Sample & Hold
(Cycles from Start of Convertion)
Conversion Time
(Cycles)
Prescaler
Reset
MUX and REFS
Update
1
2
ADC2
3
Sample &
Hold
4
is low will take the same amount of time as a single ended
5
ADC2
6
is high will take 14 ADC clock cycles due to the
7
Conversion
One Conversion
8
First
14.5
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
25
9
Conversion
10
Conversion
Complete
Complete
One Conversion
11
11
12
12
Single Ended
Conversion,
13
13
Normal
1.5
13
Next Conversion
1
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
LSB of Result
2
MUX and REFS
Update
Next Conversion
1
Prescaler
Reset
ADC2
3
Sample & Hold
2
4
Auto Triggered
equal to half the
ADC2
Convertion
4250C–CAN–03/04
13.5
. A conver-
2

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