AT90CAN128-16AE ATMEL Corporation, AT90CAN128-16AE Datasheet - Page 42

• Manufacturer Part Number: AT90CAN128-16AE
• Description: 8-bit Avr Microcontroller With 128K Bytes of Isp Flash And CAN Controller.flash (Kbytes) 128 Vcc (V) 2.7-5.5 EEPROM (Kbytes) 4 SRAM (bytes) 4K CAN (mess. Obj.) 15
• Manufacturer: ATMEL Corporation

Timer/Counter2
Oscillator
System Clock Prescaler
Clock Prescaler Register –
CLKPR
42
AT90CAN128
For AVR microcontrollers with Timer/Counter2 Oscillator pins (TOSC1 and TOSC2), the
crystal is connected directly between the pins. No external capacitors are needed. The
Oscillator is optimized for use with a 32.768 kHz watch crystal.
AT90CAN128 share the Timer/Counter2 Oscillator Pins (TOSC1 and TOSC2) with PG4
a n d P G3 . Th is me a n s th a t b o th P G 4 a n d PG3 ca n o n ly be u se d w h en th e
Timer/Counter2 Oscillator is not enable.
Applying an external clock source to TOSC1 can be done in asynchronous operation if
EXTCLK in the ASSR Register is written to logic one. See “Asynchronous operation of
the Timer/Counter2” on page 155 for futher description on selecting external clock as
input instead of a 32 kHz crystal. In this configuration, PG4 cannot be used but PG3 is
available.
The AT90CAN128 system clock can be divided by setting the Clock Prescale Register –
CLKPR. This feature can be used to decrease power consumption when the require-
ment for processing power is low. This can be used with all clock source options, and it
will affect the clock frequency of the CPU and all synchronous peripherals. clk
clk
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaniosly written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKPCE bit.
• Bit 6..0 – Reserved Bits
These bits are reserved for future use.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The divi-
sion factors are given in Table 16.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
2. Within four cycles, write the desired value to CLKPS while writing a zero to
Interrupts must be disabled when changing prescaler setting to make sure the write pro-
cedure is not interrupted.
Bit
Read/Write
Initial Value
CPU
in CLKPR to zero.
CLKPCE.
, and clk
CLKPCE
FLASH
R/W
7
0
are divided by a factor as shown in Table 16.
R
6
–
0
R
5
–
0
R
4
–
0
CLKPS3
R/W
3
CLKPS2
See Bit Description
R/W
2
CLKPS1
R/W
1
CLKPS0
R/W
0
4250C–CAN–03/04
I/O
, clk
CLKPR
ADC
,