W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 165

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

Bit 5 Complement version of OUT1# (user-designated output) signal
Bit 6 Complement version of RTS# (Request-To-Send) signal
Bit 7 Complement version of DTR# (Data-Terminal-Ready) signal
Writing 0x00 to MCR set DTR#, RTS#, OUT1# and OUT2# to logic 1s, while
writing 0x0f to MCR reset DTR#, RTS#, OUT1# and OUT2# to logic 0s.
Line Status Register (LSR)
Port address : 0xf00003fd (COM0)
Default : ---
Bits 0 RX FIFO Error
Bit 1 Transmitter Empty
Bit 2 Transmitter Holding Register Empty
W90221X version 0.6
Err_RC
VR
0
0 = RX FIFO works normally
1 = There is at least one parity error (PE), framing error (FE) or
break indication (BI)
there are no sub-
0 = Either Transmitter Holding Register (THR - TX FIFO) or
Transmitter Shift Register
1 = Both THR and TSR are empty.
0 = THR is not empty.
1 = THR is empty.
The THRE bit is set when the last data word of TX FIFO is
transferred to TSR. This bit is reset
concurrently with the loading of the THR (or TX FIFO) by the CPU.
This bit also causes the
TEMT
0xf00002fd (COM1)
1
in the FIFO. LSR[0] is cleared when CPU reads the LSR and if
sequent errors in the RX FIFO.
(TSR) are not empty.
THRE
2
BI
3
FE
4
Read only
PE
5
OE
6
Power-on
DR
7
- 165 -