W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 23

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

DQMB[0:3] (out)
MA[0:13] (out)
MD[0:31] (in/out)
CKE (out)
MCLK(out)
5.6.5 Operation Modes
MX1 Mode
MX1.5 Mode
MX2 Mode
MCLK Skew Control
W90221X version 0.6
These signals are served as DQMB function. These are input mask signals for write
cycle and output enable signals for read cycle.
These signals are used to provide the multiplexed row and column address to the
SDRAM.
These signals are used to interface to the DRAM data bus.
This signal is used to enable or disable MCLK into SDRAM.
This signal is SDRAM clock input, all SDRAM input /output signals are referenced with
MCLK rising edge.
Once DRAMTctrl2[2:3] is set to 00, memory controller frequency is same as CPUCLK.
Once DRAMTctrl2[2:3] is set to 01, Memory controller frequency is CPUCLK/1.5.
Once DRAMTctrl2[2:3] is set to 10, Memory controller frequency is CPUCLK/2.
The SDRAM's CLK and internal MEMC system clocks are adjustable for SDRAM
operating in higher clock rate (larger than 80 MHz). Three bit groups are used to define
these clocks' skew, which are one SDRAM CLK and two internal MEMC system clocks.
Following are some suggested setting when SDRAM operated in different modes: (Refer
to DRAMctrl definition for details)
MX1
MX1.5
MX2
DRAMctrl[9:11] = 110
DRAMctrl[12:14] = 010
DRAMTctrl[9:11] = 001
DRAMctrl[9:11] = 010
DRAMctrl[12:14] = 010
DRAMTctrl[9:11] = 010
DRAMctrl[9:11] = 110
DRAMctrl[12:14] = 001
DRAMTctrl[9:11] = 110
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