W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 38

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

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5.12.4 Operation Modes
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W90221X version 0.6
SIN1 (input)
SOUT1 (output)
COM1
Receiver control
Transmitter control
Set FCR[0:1] to select a proper receiver threshold level and then turn on "receiver
data available interrupt" (Irpt_RDA) by set IER[7] to logic 1.
programmed trigger level, and it will be cleared as the available data in RX-FIFO
drops below the trigger level.
As Irpt_RDA occured, the corresponding IIR bits will be set to inform the software
application that data in RX-FIFO has reached programmed threshold level.
If the received data has any errors, the "line status interrupt" (Irpt_RLS) will occur and
has higher priority than Irpt_RDA.
If "time out interrupt" (Irpt_TOR) is enable by set IER[7] and TOR[0] to logic 1s. The
Irpt_TOR will occur, if the following conditions exist:
Set IER[6] to logic 1 to enable "transmitter empty interrupt" (Irpt_THRE) before
transmitter operation.
Once the transmitter FIFO (TX-FIFO) is empty, the Irpt_THRE is triggered and the
corresponding IIR bits are set to inform the CPU to fill the TX-FIFO (maximum 16
bytes of characters).
The Irpt_THRE is reset after the CPU reads the IIR (IIR[4:7] must be 4'b0010 at that
time) or writes a character into TX-FIFO.
Irpt_RDA and Irpt_TOUT has the same interrupt priority (2nd priority) while Irpt_THRE
has a lower priority (3rd priority).
Polled Mode operation: (refer to "LSR" register descriptions located on Section 5.2.5)
No interrupts need be enabled at this mode. The CPU always polls the LSR to check
COM port status before taking any actions.
LSR[7] will be set as long as there is at least one byte in the RX-FIFO, and it is
cleared if the RX-FIFO is empty.
LSR[3:6] will specify error(s) status which is handled the same way as in the interrupt
mode operation, the IIR[4:7] is not affected since no interrupt is enabled.
LSR[2] will indicate when the TX-FIFO is empty.
Ring indicator
Serial data input from peripheral device or MODEM
Serial data output to peripheral device or MODEM
The Irpt_RDA will be triggered when the receiver FIFO (RX-FIFO) has reached its
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At least one character is in RX-FIFO
RX-FIFO is not received any data or accessed by CPU from the most recent
serial character received, and the time period, counting by baud rate bit clock,
has exceeded the value being programmed in TOR[1:7].
The Irpt_TOR and the time-out counter will be cleared as the CPU reads one
character from RX-FIFO.
The time-out counter is reset after a new character is received or after the CPU
reads the RX-FIFO.
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