W90221X Winbond Electronics Corp America, W90221X Datasheet - Page 41

• Manufacturer Part Number: W90221X
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

Figure 5.13.5.1 SSI long framing transfer
Short Framing
Figure 5.13.5.2 SSI short framing transfer
5.14 TIMER CHANNELS
5.14.1 Overview
Two 24-bit decrementing timers are implemented, corresponding to the TCR1, TICR1 and
TCR2, TICR2 independently. When the timers' interrupt enable bit is set high and the counter
decrements to zero, the timer will assert its interrupt request signal. When a timer reaches
zero, the timer hardware reloads the counter with the value from the timer initial counter
register and continues decrementing.
5.14.2 Block Diagram
W90221X version 0.6
When CFGH[3] is set to logic 0, SSI is operated in long framing mode. The following
features are included in short framing mode consists of the following features.
transmitter FIFO interrupt will be asserted (when TX-FIFO interrupt is enable) if
the available data words in transmit FIFO is lower than its threshold level.
The following figure shows a standard long framing transfer where serial word
length is 3 (CFGH[8:11] = 2), words per frame is 3 (CFGH[12:15]=2) and bits per
frame is 9 (CFGL[0:7] = 10).
The frame sync (SYNC) is asserted for one SCLK immediately before the first bit
of transmit and receive data.
The frame sync (SYNC) is asserted for one SCLK period.
All other features are the same as long framing mode.
The following figure shows a standard short framing transfer where serial word
length is 3 (CFGH[8:11] = 2), words per frame is 3 (CFGH[12:15]=2) and bits per
frame is 9 (CFGL[0:7] = 10).
SCLK
SYNC
SDI
SDO
SCLK
SYNC
SDI
SDO
D1_1
D1_1
D1_1
D1_1
D1_2
D1_2
D1_2
D1_2
D1_3
D1_3
D1_3
D1_3
D2_1
D2_1
D2_1
D2_1
D2_2
D2_2
D2_2
D2_2
D2_3
D2_3
D2_3
D2_3
D3_1
D3_1
D3_1
D3_1
D3_2
D3_2
D3_2
D3_2
D3_3
D3_3
D3_3
D3_3
D1_1
D1_1
D1_1
D1_1
D1_2
D1_2
D1_2
D1_2
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